1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013 Google Inc. 3*4882a593Smuzhiyun * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _BAYTRAIL_IRQ_H_ 11*4882a593Smuzhiyun #define _BAYTRAIL_IRQ_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define PIRQA_APIC_IRQ 16 14*4882a593Smuzhiyun #define PIRQB_APIC_IRQ 17 15*4882a593Smuzhiyun #define PIRQC_APIC_IRQ 18 16*4882a593Smuzhiyun #define PIRQD_APIC_IRQ 19 17*4882a593Smuzhiyun #define PIRQE_APIC_IRQ 20 18*4882a593Smuzhiyun #define PIRQF_APIC_IRQ 21 19*4882a593Smuzhiyun #define PIRQG_APIC_IRQ 22 20*4882a593Smuzhiyun #define PIRQH_APIC_IRQ 23 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* The below IRQs are for when devices are in ACPI mode */ 23*4882a593Smuzhiyun #define LPE_DMA0_IRQ 24 24*4882a593Smuzhiyun #define LPE_DMA1_IRQ 25 25*4882a593Smuzhiyun #define LPE_SSP0_IRQ 26 26*4882a593Smuzhiyun #define LPE_SSP1_IRQ 27 27*4882a593Smuzhiyun #define LPE_SSP2_IRQ 28 28*4882a593Smuzhiyun #define LPE_IPC2HOST_IRQ 29 29*4882a593Smuzhiyun #define LPSS_I2C1_IRQ 32 30*4882a593Smuzhiyun #define LPSS_I2C2_IRQ 33 31*4882a593Smuzhiyun #define LPSS_I2C3_IRQ 34 32*4882a593Smuzhiyun #define LPSS_I2C4_IRQ 35 33*4882a593Smuzhiyun #define LPSS_I2C5_IRQ 36 34*4882a593Smuzhiyun #define LPSS_I2C6_IRQ 37 35*4882a593Smuzhiyun #define LPSS_I2C7_IRQ 38 36*4882a593Smuzhiyun #define LPSS_HSUART1_IRQ 39 37*4882a593Smuzhiyun #define LPSS_HSUART2_IRQ 40 38*4882a593Smuzhiyun #define LPSS_SPI_IRQ 41 39*4882a593Smuzhiyun #define LPSS_DMA1_IRQ 42 40*4882a593Smuzhiyun #define LPSS_DMA2_IRQ 43 41*4882a593Smuzhiyun #define SCC_EMMC_IRQ 44 42*4882a593Smuzhiyun #define SCC_SDIO_IRQ 46 43*4882a593Smuzhiyun #define SCC_SD_IRQ 47 44*4882a593Smuzhiyun #define GPIO_NC_IRQ 48 45*4882a593Smuzhiyun #define GPIO_SC_IRQ 49 46*4882a593Smuzhiyun #define GPIO_SUS_IRQ 50 47*4882a593Smuzhiyun /* GPIO direct / dedicated IRQs */ 48*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ_0 51 49*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ_1 52 50*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ_2 53 51*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ_3 54 52*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ_4 55 53*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ_5 56 54*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ_6 57 55*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ_7 58 56*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ_8 59 57*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ_9 60 58*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ_10 61 59*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ_11 62 60*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ_12 63 61*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ_13 64 62*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ_14 65 63*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ_15 66 64*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ_0 67 65*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ_1 68 66*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ_2 69 67*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ_3 70 68*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ_4 71 69*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ_5 72 70*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ_6 73 71*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ_7 74 72*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ_8 75 73*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ_9 76 74*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ_10 77 75*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ_11 78 76*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ_12 79 77*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ_13 80 78*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ_14 81 79*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ_15 82 80*4882a593Smuzhiyun /* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */ 81*4882a593Smuzhiyun #define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot 82*4882a593Smuzhiyun #define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot 83*4882a593Smuzhiyun #define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot) 84*4882a593Smuzhiyun #define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #endif /* _BAYTRAIL_IRQ_H_ */ 87