1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013 Google Inc. 3*4882a593Smuzhiyun * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _DEVICE_H_ 11*4882a593Smuzhiyun #define _DEVICE_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * Internal PCI device numbers within the SoC. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * Note it must start with 0x_ prefix, as the device number macro will be 17*4882a593Smuzhiyun * included in the ACPI ASL files (see irq_helper.h and irq_route.h). 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* SoC transaction router */ 21*4882a593Smuzhiyun #define SOC_DEV 0x00 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* Graphics and Display */ 24*4882a593Smuzhiyun #define GFX_DEV 0x02 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* MIPI */ 27*4882a593Smuzhiyun #define MIPI_DEV 0x03 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* EMMC Port */ 30*4882a593Smuzhiyun #define EMMC_DEV 0x10 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* SDIO Port */ 33*4882a593Smuzhiyun #define SDIO_DEV 0x11 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* SD Port */ 36*4882a593Smuzhiyun #define SD_DEV 0x12 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* SATA */ 39*4882a593Smuzhiyun #define SATA_DEV 0x13 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* xHCI */ 42*4882a593Smuzhiyun #define XHCI_DEV 0x14 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* LPE Audio */ 45*4882a593Smuzhiyun #define LPE_DEV 0x15 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* OTG */ 48*4882a593Smuzhiyun #define OTG_DEV 0x16 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* MMC45 Port */ 51*4882a593Smuzhiyun #define MMC45_DEV 0x17 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Serial IO 1 */ 54*4882a593Smuzhiyun #define SIO1_DEV 0x18 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Trusted Execution Engine */ 57*4882a593Smuzhiyun #define TXE_DEV 0x1a 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* HD Audio */ 60*4882a593Smuzhiyun #define HDA_DEV 0x1b 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* PCIe Ports */ 63*4882a593Smuzhiyun #define PCIE_DEV 0x1c 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* EHCI */ 66*4882a593Smuzhiyun #define EHCI_DEV 0x1d 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* Serial IO 2 */ 69*4882a593Smuzhiyun #define SIO2_DEV 0x1e 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Platform Controller Unit */ 72*4882a593Smuzhiyun #define PCU_DEV 0x1f 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif /* _DEVICE_H_ */ 75