1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2014 Google Inc. 3*4882a593Smuzhiyun * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Modified from coreboot src/soc/intel/baytrail/acpi/xhci.asl 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/* XHCI Controller 0:14.0 */ 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunDevice (XHCI) 13*4882a593Smuzhiyun{ 14*4882a593Smuzhiyun Name(_ADR, 0x00140000) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Power Resources for Wake */ 17*4882a593Smuzhiyun Name(_PRW, Package() { 13, 3 }) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Highest D state in S3 state */ 20*4882a593Smuzhiyun Name(_S3D, 3) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun Device (RHUB) 23*4882a593Smuzhiyun { 24*4882a593Smuzhiyun Name(_ADR, 0x00000000) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun Device (PRT1) { Name(_ADR, 1) } /* USB Port 0 */ 27*4882a593Smuzhiyun Device (PRT2) { Name(_ADR, 2) } /* USB Port 1 */ 28*4882a593Smuzhiyun Device (PRT3) { Name(_ADR, 3) } /* USB Port 2 */ 29*4882a593Smuzhiyun Device (PRT4) { Name(_ADR, 4) } /* USB Port 3 */ 30*4882a593Smuzhiyun } 31*4882a593Smuzhiyun} 32