1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2007-2009 coresystems GmbH 3*4882a593Smuzhiyun * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Modified from coreboot src/soc/intel/baytrail/acpi/usb.asl 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/* EHCI Controller 0:1d.0 */ 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunDevice (EHC1) 13*4882a593Smuzhiyun{ 14*4882a593Smuzhiyun Name(_ADR, 0x001d0000) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Power Resources for Wake */ 17*4882a593Smuzhiyun Name(_PRW, Package() { 13, 4 }) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Highest D state in S3 state */ 20*4882a593Smuzhiyun Name(_S3D, 2) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Highest D state in S4 state */ 23*4882a593Smuzhiyun Name(_S4D, 2) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun Device (HUB7) 26*4882a593Smuzhiyun { 27*4882a593Smuzhiyun Name(_ADR, 0x00000000) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun Device(PRT1) { Name(_ADR, 1) } /* USB Port 0 */ 30*4882a593Smuzhiyun Device(PRT2) { Name(_ADR, 2) } /* USB Port 1 */ 31*4882a593Smuzhiyun Device(PRT3) { Name(_ADR, 3) } /* USB Port 2 */ 32*4882a593Smuzhiyun Device(PRT4) { Name(_ADR, 4) } /* USB Port 3 */ 33*4882a593Smuzhiyun } 34*4882a593Smuzhiyun} 35