1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (c) 2017 Intel Corporation 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <dt-bindings/gpio/x86-gpio.h> 10*4882a593Smuzhiyun#include <dt-bindings/interrupt-router/intel-irq.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/include/ "skeleton.dtsi" 13*4882a593Smuzhiyun/include/ "rtc.dtsi" 14*4882a593Smuzhiyun/include/ "tsc_timer.dtsi" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun/ { 17*4882a593Smuzhiyun model = "Intel Edison"; 18*4882a593Smuzhiyun compatible = "intel,edison"; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun aliases { 21*4882a593Smuzhiyun serial0 = &serial0; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun chosen { 25*4882a593Smuzhiyun stdout-path = &serial0; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun cpus { 29*4882a593Smuzhiyun #address-cells = <1>; 30*4882a593Smuzhiyun #size-cells = <0>; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun cpu@0 { 33*4882a593Smuzhiyun device_type = "cpu"; 34*4882a593Smuzhiyun compatible = "cpu-x86"; 35*4882a593Smuzhiyun reg = <0>; 36*4882a593Smuzhiyun intel,apic-id = <0>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun cpu@1 { 40*4882a593Smuzhiyun device_type = "cpu"; 41*4882a593Smuzhiyun compatible = "cpu-x86"; 42*4882a593Smuzhiyun reg = <1>; 43*4882a593Smuzhiyun intel,apic-id = <2>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun pci { 48*4882a593Smuzhiyun compatible = "pci-x86"; 49*4882a593Smuzhiyun #address-cells = <3>; 50*4882a593Smuzhiyun #size-cells = <2>; 51*4882a593Smuzhiyun u-boot,dm-pre-reloc; 52*4882a593Smuzhiyun ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 53*4882a593Smuzhiyun 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 54*4882a593Smuzhiyun 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun serial0: serial@ff010180 { 58*4882a593Smuzhiyun compatible = "intel,mid-uart"; 59*4882a593Smuzhiyun reg = <0xff010180 0x100>; 60*4882a593Smuzhiyun reg-shift = <0>; 61*4882a593Smuzhiyun clock-frequency = <29491200>; 62*4882a593Smuzhiyun current-speed = <115200>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun emmc: mmc@ff3fc000 { 66*4882a593Smuzhiyun compatible = "intel,sdhci-tangier"; 67*4882a593Smuzhiyun reg = <0xff3fc000 0x1000>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun/* 71*4882a593Smuzhiyun * FIXME: For now U-Boot DM model doesn't allow to power up this controller. 72*4882a593Smuzhiyun * Enabling it will make U-Boot hang. 73*4882a593Smuzhiyun * 74*4882a593Smuzhiyun sdcard: mmc@ff3fa000 { 75*4882a593Smuzhiyun compatible = "intel,sdhci-tangier"; 76*4882a593Smuzhiyun reg = <0xff3fa000 0x1000>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun */ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun pmu: power@ff00b000 { 81*4882a593Smuzhiyun compatible = "intel,pmu-mid"; 82*4882a593Smuzhiyun reg = <0xff00b000 0x1000>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun scu: ipc@ff009000 { 86*4882a593Smuzhiyun compatible = "intel,scu-ipc"; 87*4882a593Smuzhiyun reg = <0xff009000 0x1000>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun}; 90