1 /*
2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 * Copyright (C) 2015 Google, Inc
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <asm/io.h>
11 #include <asm/irq.h>
12 #include <asm/pci.h>
13 #include <asm/arch/device.h>
14 #include <asm/arch/tnc.h>
15
queensbay_irq_router_probe(struct udevice * dev)16 int queensbay_irq_router_probe(struct udevice *dev)
17 {
18 struct tnc_rcba *rcba;
19 u32 base;
20
21 dm_pci_read_config32(dev->parent, LPC_RCBA, &base);
22 base &= ~MEM_BAR_EN;
23 rcba = (struct tnc_rcba *)base;
24
25 /* Make sure all internal PCI devices are using INTA */
26 writel(INTA, &rcba->d02ip);
27 writel(INTA, &rcba->d03ip);
28 writel(INTA, &rcba->d27ip);
29 writel(INTA, &rcba->d31ip);
30 writel(INTA, &rcba->d23ip);
31 writel(INTA, &rcba->d24ip);
32 writel(INTA, &rcba->d25ip);
33 writel(INTA, &rcba->d26ip);
34
35 /*
36 * Route TunnelCreek PCI device interrupt pin to PIRQ
37 *
38 * Since PCIe downstream ports received INTx are routed to PIRQ
39 * A/B/C/D directly and not configurable, we have to route PCIe
40 * root ports' INTx to PIRQ A/B/C/D as well. For other devices
41 * on TunneCreek, route them to PIRQ E/F/G/H.
42 */
43 writew(PIRQE, &rcba->d02ir);
44 writew(PIRQF, &rcba->d03ir);
45 writew(PIRQG, &rcba->d27ir);
46 writew(PIRQH, &rcba->d31ir);
47 writew(PIRQA, &rcba->d23ir);
48 writew(PIRQB, &rcba->d24ir);
49 writew(PIRQC, &rcba->d25ir);
50 writew(PIRQD, &rcba->d26ir);
51
52 return irq_router_common_init(dev);
53 }
54
55 static const struct udevice_id queensbay_irq_router_ids[] = {
56 { .compatible = "intel,queensbay-irq-router" },
57 { }
58 };
59
60 U_BOOT_DRIVER(queensbay_irq_router_drv) = {
61 .name = "queensbay_intel_irq",
62 .id = UCLASS_IRQ,
63 .of_match = queensbay_irq_router_ids,
64 .probe = queensbay_irq_router_probe,
65 };
66