1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3*4882a593Smuzhiyun * Copyright (C) 2015 Google, Inc
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <dm.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/irq.h>
12*4882a593Smuzhiyun #include <asm/pci.h>
13*4882a593Smuzhiyun #include <asm/arch/device.h>
14*4882a593Smuzhiyun #include <asm/arch/tnc.h>
15*4882a593Smuzhiyun
queensbay_irq_router_probe(struct udevice * dev)16*4882a593Smuzhiyun int queensbay_irq_router_probe(struct udevice *dev)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun struct tnc_rcba *rcba;
19*4882a593Smuzhiyun u32 base;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun dm_pci_read_config32(dev->parent, LPC_RCBA, &base);
22*4882a593Smuzhiyun base &= ~MEM_BAR_EN;
23*4882a593Smuzhiyun rcba = (struct tnc_rcba *)base;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Make sure all internal PCI devices are using INTA */
26*4882a593Smuzhiyun writel(INTA, &rcba->d02ip);
27*4882a593Smuzhiyun writel(INTA, &rcba->d03ip);
28*4882a593Smuzhiyun writel(INTA, &rcba->d27ip);
29*4882a593Smuzhiyun writel(INTA, &rcba->d31ip);
30*4882a593Smuzhiyun writel(INTA, &rcba->d23ip);
31*4882a593Smuzhiyun writel(INTA, &rcba->d24ip);
32*4882a593Smuzhiyun writel(INTA, &rcba->d25ip);
33*4882a593Smuzhiyun writel(INTA, &rcba->d26ip);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun * Route TunnelCreek PCI device interrupt pin to PIRQ
37*4882a593Smuzhiyun *
38*4882a593Smuzhiyun * Since PCIe downstream ports received INTx are routed to PIRQ
39*4882a593Smuzhiyun * A/B/C/D directly and not configurable, we have to route PCIe
40*4882a593Smuzhiyun * root ports' INTx to PIRQ A/B/C/D as well. For other devices
41*4882a593Smuzhiyun * on TunneCreek, route them to PIRQ E/F/G/H.
42*4882a593Smuzhiyun */
43*4882a593Smuzhiyun writew(PIRQE, &rcba->d02ir);
44*4882a593Smuzhiyun writew(PIRQF, &rcba->d03ir);
45*4882a593Smuzhiyun writew(PIRQG, &rcba->d27ir);
46*4882a593Smuzhiyun writew(PIRQH, &rcba->d31ir);
47*4882a593Smuzhiyun writew(PIRQA, &rcba->d23ir);
48*4882a593Smuzhiyun writew(PIRQB, &rcba->d24ir);
49*4882a593Smuzhiyun writew(PIRQC, &rcba->d25ir);
50*4882a593Smuzhiyun writew(PIRQD, &rcba->d26ir);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return irq_router_common_init(dev);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static const struct udevice_id queensbay_irq_router_ids[] = {
56*4882a593Smuzhiyun { .compatible = "intel,queensbay-irq-router" },
57*4882a593Smuzhiyun { }
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun U_BOOT_DRIVER(queensbay_irq_router_drv) = {
61*4882a593Smuzhiyun .name = "queensbay_intel_irq",
62*4882a593Smuzhiyun .id = UCLASS_IRQ,
63*4882a593Smuzhiyun .of_match = queensbay_irq_router_ids,
64*4882a593Smuzhiyun .probe = queensbay_irq_router_probe,
65*4882a593Smuzhiyun };
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