xref: /OK3568_Linux_fs/u-boot/arch/x86/cpu/quark/car.S (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier:	GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <config.h>
8*4882a593Smuzhiyun#include <asm/pci.h>
9*4882a593Smuzhiyun#include <asm/post.h>
10*4882a593Smuzhiyun#include <asm/arch/quark.h>
11*4882a593Smuzhiyun#include <asm/arch/msg_port.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun.globl car_init
14*4882a593Smuzhiyuncar_init:
15*4882a593Smuzhiyun	post_code(POST_CAR_START)
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	/*
18*4882a593Smuzhiyun	 * Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is
19*4882a593Smuzhiyun	 * initialized by hardware. eSRAM is the ideal place to be used
20*4882a593Smuzhiyun	 * for Cache-As-RAM (CAR) before system memory is available.
21*4882a593Smuzhiyun	 *
22*4882a593Smuzhiyun	 * Relocate this eSRAM to a suitable location in the physical
23*4882a593Smuzhiyun	 * memory map and enable it.
24*4882a593Smuzhiyun	 */
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	/* Host Memory Bound Register P03h:R08h */
27*4882a593Smuzhiyun	mov	$((MSG_PORT_HOST_BRIDGE << 16) | (HM_BOUND << 8)), %eax
28*4882a593Smuzhiyun	mov	$(DRAM_BASE + DRAM_MAX_SIZE + ESRAM_SIZE), %edx
29*4882a593Smuzhiyun	lea	1f, %esp
30*4882a593Smuzhiyun	jmp	msg_port_write
31*4882a593Smuzhiyun1:
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun	/* eSRAM Block Page Control Register P05h:R82h */
34*4882a593Smuzhiyun	mov	$((MSG_PORT_MEM_MGR << 16) | (ESRAM_BLK_CTRL << 8)), %eax
35*4882a593Smuzhiyun	mov	$(ESRAM_BLOCK_MODE | (CONFIG_ESRAM_BASE >> 24)), %edx
36*4882a593Smuzhiyun	lea	2f, %esp
37*4882a593Smuzhiyun	jmp	msg_port_write
38*4882a593Smuzhiyun2:
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun	post_code(POST_CAR_CPU_CACHE)
41*4882a593Smuzhiyun	jmp	car_init_ret
42*4882a593Smuzhiyun
43*4882a593Smuzhiyunmsg_port_read:
44*4882a593Smuzhiyun	/*
45*4882a593Smuzhiyun	 * Parameter:
46*4882a593Smuzhiyun	 *   eax[23:16] - Message Port ID
47*4882a593Smuzhiyun	 *   eax[15:08] - Register Address
48*4882a593Smuzhiyun	 *
49*4882a593Smuzhiyun	 * Return Value:
50*4882a593Smuzhiyun	 *   eax - Message Port Register value
51*4882a593Smuzhiyun	 *
52*4882a593Smuzhiyun	 * Return Address: esp
53*4882a593Smuzhiyun	 */
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun	or	$((MSG_OP_READ << 24) | MSG_BYTE_ENABLE), %eax
56*4882a593Smuzhiyun	mov	%eax, %ebx
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun	/* Write MCR B0:D0:F0:RD0 */
59*4882a593Smuzhiyun	mov	$(PCI_CFG_EN | MSG_CTRL_REG), %eax
60*4882a593Smuzhiyun	mov	$PCI_REG_ADDR, %dx
61*4882a593Smuzhiyun	out	%eax, %dx
62*4882a593Smuzhiyun	mov	$PCI_REG_DATA, %dx
63*4882a593Smuzhiyun	mov	%ebx, %eax
64*4882a593Smuzhiyun	out	%eax, %dx
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun	/* Read MDR B0:D0:F0:RD4 */
67*4882a593Smuzhiyun	mov	$(PCI_CFG_EN | MSG_DATA_REG), %eax
68*4882a593Smuzhiyun	mov	$PCI_REG_ADDR, %dx
69*4882a593Smuzhiyun	out	%eax, %dx
70*4882a593Smuzhiyun	mov	$PCI_REG_DATA, %dx
71*4882a593Smuzhiyun	in	%dx, %eax
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun	jmp	*%esp
74*4882a593Smuzhiyun
75*4882a593Smuzhiyunmsg_port_write:
76*4882a593Smuzhiyun	/*
77*4882a593Smuzhiyun	 * Parameter:
78*4882a593Smuzhiyun	 *   eax[23:16] - Message Port ID
79*4882a593Smuzhiyun	 *   eax[15:08] - Register Address
80*4882a593Smuzhiyun	 *   edx        - Message Port Register value to write
81*4882a593Smuzhiyun	 *
82*4882a593Smuzhiyun	 * Return Address: esp
83*4882a593Smuzhiyun	 */
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun	or	$((MSG_OP_WRITE << 24) | MSG_BYTE_ENABLE), %eax
86*4882a593Smuzhiyun	mov	%eax, %esi
87*4882a593Smuzhiyun	mov	%edx, %edi
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun	/* Write MDR B0:D0:F0:RD4 */
90*4882a593Smuzhiyun	mov	$(PCI_CFG_EN | MSG_DATA_REG), %eax
91*4882a593Smuzhiyun	mov	$PCI_REG_ADDR, %dx
92*4882a593Smuzhiyun	out	%eax, %dx
93*4882a593Smuzhiyun	mov	$PCI_REG_DATA, %dx
94*4882a593Smuzhiyun	mov	%edi, %eax
95*4882a593Smuzhiyun	out	%eax, %dx
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun	/* Write MCR B0:D0:F0:RD0 */
98*4882a593Smuzhiyun	mov	$(PCI_CFG_EN | MSG_CTRL_REG), %eax
99*4882a593Smuzhiyun	mov	$PCI_REG_ADDR, %dx
100*4882a593Smuzhiyun	out	%eax, %dx
101*4882a593Smuzhiyun	mov	$PCI_REG_DATA, %dx
102*4882a593Smuzhiyun	mov	%esi, %eax
103*4882a593Smuzhiyun	out	%eax, %dx
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun	jmp	*%esp
106