1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2011 The Chromium OS Authors.
3*4882a593Smuzhiyun * (C) Copyright 2008,2009
4*4882a593Smuzhiyun * Graeme Russ, <graeme.russ@gmail.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * (C) Copyright 2002
7*4882a593Smuzhiyun * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <dm.h>
14*4882a593Smuzhiyun #include <errno.h>
15*4882a593Smuzhiyun #include <malloc.h>
16*4882a593Smuzhiyun #include <pci.h>
17*4882a593Smuzhiyun #include <asm/io.h>
18*4882a593Smuzhiyun #include <asm/pci.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
21*4882a593Smuzhiyun
pci_x86_read_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong * valuep,enum pci_size_t size)22*4882a593Smuzhiyun int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
23*4882a593Smuzhiyun ulong *valuep, enum pci_size_t size)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
26*4882a593Smuzhiyun switch (size) {
27*4882a593Smuzhiyun case PCI_SIZE_8:
28*4882a593Smuzhiyun *valuep = inb(PCI_REG_DATA + (offset & 3));
29*4882a593Smuzhiyun break;
30*4882a593Smuzhiyun case PCI_SIZE_16:
31*4882a593Smuzhiyun *valuep = inw(PCI_REG_DATA + (offset & 2));
32*4882a593Smuzhiyun break;
33*4882a593Smuzhiyun case PCI_SIZE_32:
34*4882a593Smuzhiyun *valuep = inl(PCI_REG_DATA);
35*4882a593Smuzhiyun break;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun return 0;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
pci_x86_write_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)41*4882a593Smuzhiyun int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
42*4882a593Smuzhiyun ulong value, enum pci_size_t size)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
45*4882a593Smuzhiyun switch (size) {
46*4882a593Smuzhiyun case PCI_SIZE_8:
47*4882a593Smuzhiyun outb(value, PCI_REG_DATA + (offset & 3));
48*4882a593Smuzhiyun break;
49*4882a593Smuzhiyun case PCI_SIZE_16:
50*4882a593Smuzhiyun outw(value, PCI_REG_DATA + (offset & 2));
51*4882a593Smuzhiyun break;
52*4882a593Smuzhiyun case PCI_SIZE_32:
53*4882a593Smuzhiyun outl(value, PCI_REG_DATA);
54*4882a593Smuzhiyun break;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return 0;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
pci_assign_irqs(int bus,int device,u8 irq[4])60*4882a593Smuzhiyun void pci_assign_irqs(int bus, int device, u8 irq[4])
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun pci_dev_t bdf;
63*4882a593Smuzhiyun int func;
64*4882a593Smuzhiyun u16 vendor;
65*4882a593Smuzhiyun u8 pin, line;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun for (func = 0; func < 8; func++) {
68*4882a593Smuzhiyun bdf = PCI_BDF(bus, device, func);
69*4882a593Smuzhiyun pci_read_config16(bdf, PCI_VENDOR_ID, &vendor);
70*4882a593Smuzhiyun if (vendor == 0xffff || vendor == 0x0000)
71*4882a593Smuzhiyun continue;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun pci_read_config8(bdf, PCI_INTERRUPT_PIN, &pin);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* PCI spec says all values except 1..4 are reserved */
76*4882a593Smuzhiyun if ((pin < 1) || (pin > 4))
77*4882a593Smuzhiyun continue;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun line = irq[pin - 1];
80*4882a593Smuzhiyun if (!line)
81*4882a593Smuzhiyun continue;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n",
84*4882a593Smuzhiyun line, bus, device, func, 'A' + pin - 1);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun pci_write_config8(bdf, PCI_INTERRUPT_LINE, line);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun }
89