1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2016 Google, Inc
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <errno.h>
10*4882a593Smuzhiyun #include <fdtdec.h>
11*4882a593Smuzhiyun #include <pch.h>
12*4882a593Smuzhiyun #include <pci.h>
13*4882a593Smuzhiyun #include <asm/intel_regs.h>
14*4882a593Smuzhiyun #include <asm/io.h>
15*4882a593Smuzhiyun #include <asm/lpc_common.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* Enable Prefetching and Caching */
enable_spi_prefetch(struct udevice * pch)20*4882a593Smuzhiyun static void enable_spi_prefetch(struct udevice *pch)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun u8 reg8;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun dm_pci_read_config8(pch, 0xdc, ®8);
25*4882a593Smuzhiyun reg8 &= ~(3 << 2);
26*4882a593Smuzhiyun reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
27*4882a593Smuzhiyun dm_pci_write_config8(pch, 0xdc, reg8);
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
enable_port80_on_lpc(struct udevice * pch)30*4882a593Smuzhiyun static void enable_port80_on_lpc(struct udevice *pch)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun /* Enable port 80 POST on LPC */
33*4882a593Smuzhiyun dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1);
34*4882a593Smuzhiyun clrbits_le32(RCB_REG(GCS), 4);
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /**
38*4882a593Smuzhiyun * lpc_early_init() - set up LPC serial ports and other early things
39*4882a593Smuzhiyun *
40*4882a593Smuzhiyun * @dev: LPC device
41*4882a593Smuzhiyun * @return 0 if OK, -ve on error
42*4882a593Smuzhiyun */
lpc_common_early_init(struct udevice * dev)43*4882a593Smuzhiyun int lpc_common_early_init(struct udevice *dev)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun struct udevice *pch = dev->parent;
46*4882a593Smuzhiyun struct reg_info {
47*4882a593Smuzhiyun u32 base;
48*4882a593Smuzhiyun u32 size;
49*4882a593Smuzhiyun } values[4], *ptr;
50*4882a593Smuzhiyun int count;
51*4882a593Smuzhiyun int i;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun count = fdtdec_get_int_array_count(gd->fdt_blob, dev_of_offset(dev),
54*4882a593Smuzhiyun "intel,gen-dec", (u32 *)values,
55*4882a593Smuzhiyun sizeof(values) / sizeof(u32));
56*4882a593Smuzhiyun if (count < 0)
57*4882a593Smuzhiyun return -EINVAL;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Set COM1/COM2 decode range */
60*4882a593Smuzhiyun dm_pci_write_config16(pch, LPC_IO_DEC, 0x0010);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
63*4882a593Smuzhiyun dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
64*4882a593Smuzhiyun GAMEL_LPC_EN | COMA_LPC_EN);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Write all registers but use 0 if we run out of data */
67*4882a593Smuzhiyun count = count * sizeof(u32) / sizeof(values[0]);
68*4882a593Smuzhiyun for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
69*4882a593Smuzhiyun u32 reg = 0;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun if (i < count)
72*4882a593Smuzhiyun reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
73*4882a593Smuzhiyun dm_pci_write_config32(pch, LPC_GENX_DEC(i), reg);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun enable_spi_prefetch(pch);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* This is already done in start.S, but let's do it in C */
79*4882a593Smuzhiyun enable_port80_on_lpc(pch);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return 0;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
lpc_set_spi_protect(struct udevice * dev,int bios_ctrl,bool protect)84*4882a593Smuzhiyun int lpc_set_spi_protect(struct udevice *dev, int bios_ctrl, bool protect)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun uint8_t bios_cntl;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
89*4882a593Smuzhiyun dm_pci_read_config8(dev, bios_ctrl, &bios_cntl);
90*4882a593Smuzhiyun if (protect) {
91*4882a593Smuzhiyun bios_cntl &= ~BIOS_CTRL_BIOSWE;
92*4882a593Smuzhiyun bios_cntl |= BIT(5);
93*4882a593Smuzhiyun } else {
94*4882a593Smuzhiyun bios_cntl |= BIOS_CTRL_BIOSWE;
95*4882a593Smuzhiyun bios_cntl &= ~BIT(5);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun dm_pci_write_config8(dev, bios_ctrl, bios_cntl);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun return 0;
100*4882a593Smuzhiyun }
101