1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2016 Google, Inc
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <errno.h>
10*4882a593Smuzhiyun #include <asm/cpu_common.h>
11*4882a593Smuzhiyun #include <asm/intel_regs.h>
12*4882a593Smuzhiyun #include <asm/lapic.h>
13*4882a593Smuzhiyun #include <asm/lpc_common.h>
14*4882a593Smuzhiyun #include <asm/msr.h>
15*4882a593Smuzhiyun #include <asm/mtrr.h>
16*4882a593Smuzhiyun #include <asm/post.h>
17*4882a593Smuzhiyun #include <asm/microcode.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
20*4882a593Smuzhiyun
report_bist_failure(void)21*4882a593Smuzhiyun static int report_bist_failure(void)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun if (gd->arch.bist != 0) {
24*4882a593Smuzhiyun post_code(POST_BIST_FAILURE);
25*4882a593Smuzhiyun printf("BIST failed: %08x\n", gd->arch.bist);
26*4882a593Smuzhiyun return -EFAULT;
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun return 0;
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
cpu_common_init(void)32*4882a593Smuzhiyun int cpu_common_init(void)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun struct udevice *dev, *lpc;
35*4882a593Smuzhiyun int ret;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Halt if there was a built in self test failure */
38*4882a593Smuzhiyun ret = report_bist_failure();
39*4882a593Smuzhiyun if (ret)
40*4882a593Smuzhiyun return ret;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun enable_lapic();
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun ret = microcode_update_intel();
45*4882a593Smuzhiyun if (ret && ret != -EEXIST) {
46*4882a593Smuzhiyun debug("%s: Microcode update failure (err=%d)\n", __func__, ret);
47*4882a593Smuzhiyun return ret;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* Enable upper 128bytes of CMOS */
51*4882a593Smuzhiyun writel(1 << 2, RCB_REG(RC));
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Early chipset init required before RAM init can work */
54*4882a593Smuzhiyun uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun ret = uclass_first_device(UCLASS_LPC, &lpc);
57*4882a593Smuzhiyun if (ret)
58*4882a593Smuzhiyun return ret;
59*4882a593Smuzhiyun if (!lpc)
60*4882a593Smuzhiyun return -ENODEV;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* Cause the SATA device to do its early init */
63*4882a593Smuzhiyun uclass_first_device(UCLASS_AHCI, &dev);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun return 0;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
cpu_set_flex_ratio_to_tdp_nominal(void)68*4882a593Smuzhiyun int cpu_set_flex_ratio_to_tdp_nominal(void)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun msr_t flex_ratio, msr;
71*4882a593Smuzhiyun u8 nominal_ratio;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* Check for Flex Ratio support */
74*4882a593Smuzhiyun flex_ratio = msr_read(MSR_FLEX_RATIO);
75*4882a593Smuzhiyun if (!(flex_ratio.lo & FLEX_RATIO_EN))
76*4882a593Smuzhiyun return -EINVAL;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* Check for >0 configurable TDPs */
79*4882a593Smuzhiyun msr = msr_read(MSR_PLATFORM_INFO);
80*4882a593Smuzhiyun if (((msr.hi >> 1) & 3) == 0)
81*4882a593Smuzhiyun return -EINVAL;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* Use nominal TDP ratio for flex ratio */
84*4882a593Smuzhiyun msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
85*4882a593Smuzhiyun nominal_ratio = msr.lo & 0xff;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* See if flex ratio is already set to nominal TDP ratio */
88*4882a593Smuzhiyun if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
89*4882a593Smuzhiyun return 0;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* Set flex ratio to nominal TDP ratio */
92*4882a593Smuzhiyun flex_ratio.lo &= ~0xff00;
93*4882a593Smuzhiyun flex_ratio.lo |= nominal_ratio << 8;
94*4882a593Smuzhiyun flex_ratio.lo |= FLEX_RATIO_LOCK;
95*4882a593Smuzhiyun msr_write(MSR_FLEX_RATIO, flex_ratio);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* Set flex ratio in soft reset data register bits 11:6 */
98*4882a593Smuzhiyun clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
99*4882a593Smuzhiyun (nominal_ratio & 0x3f) << 6);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun debug("CPU: Soft reset to set up flex ratio\n");
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* Set soft reset control to use register value */
104*4882a593Smuzhiyun setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* Issue warm reset, will be "CPU only" due to soft reset data */
107*4882a593Smuzhiyun outb(0x0, IO_PORT_RESET);
108*4882a593Smuzhiyun outb(SYS_RST | RST_CPU, IO_PORT_RESET);
109*4882a593Smuzhiyun cpu_hlt();
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* Not reached */
112*4882a593Smuzhiyun return -EINVAL;
113*4882a593Smuzhiyun }
114