1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * From coreboot src/soc/intel/broadwell/romstage/power_state.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2016 Google, Inc.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <pci.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <asm/intel_regs.h>
13*4882a593Smuzhiyun #include <asm/arch/iomap.h>
14*4882a593Smuzhiyun #include <asm/arch/lpc.h>
15*4882a593Smuzhiyun #include <asm/arch/pch.h>
16*4882a593Smuzhiyun #include <asm/arch/pm.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* Return 0, 3, or 5 to indicate the previous sleep state. */
prev_sleep_state(struct chipset_power_state * ps)19*4882a593Smuzhiyun static int prev_sleep_state(struct chipset_power_state *ps)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun /* Default to S0. */
22*4882a593Smuzhiyun int prev_sleep_state = SLEEP_STATE_S0;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun if (ps->pm1_sts & WAK_STS) {
25*4882a593Smuzhiyun switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
26*4882a593Smuzhiyun #if CONFIG_HAVE_ACPI_RESUME
27*4882a593Smuzhiyun case SLP_TYP_S3:
28*4882a593Smuzhiyun prev_sleep_state = SLEEP_STATE_S3;
29*4882a593Smuzhiyun break;
30*4882a593Smuzhiyun #endif
31*4882a593Smuzhiyun case SLP_TYP_S5:
32*4882a593Smuzhiyun prev_sleep_state = SLEEP_STATE_S5;
33*4882a593Smuzhiyun break;
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun /* Clear SLP_TYP. */
36*4882a593Smuzhiyun outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR))
40*4882a593Smuzhiyun prev_sleep_state = SLEEP_STATE_S5;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return prev_sleep_state;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
dump_power_state(struct chipset_power_state * ps)45*4882a593Smuzhiyun static void dump_power_state(struct chipset_power_state *ps)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun debug("PM1_STS: %04x\n", ps->pm1_sts);
48*4882a593Smuzhiyun debug("PM1_EN: %04x\n", ps->pm1_en);
49*4882a593Smuzhiyun debug("PM1_CNT: %08x\n", ps->pm1_cnt);
50*4882a593Smuzhiyun debug("TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun debug("GPE0_STS: %08x %08x %08x %08x\n",
53*4882a593Smuzhiyun ps->gpe0_sts[0], ps->gpe0_sts[1],
54*4882a593Smuzhiyun ps->gpe0_sts[2], ps->gpe0_sts[3]);
55*4882a593Smuzhiyun debug("GPE0_EN: %08x %08x %08x %08x\n",
56*4882a593Smuzhiyun ps->gpe0_en[0], ps->gpe0_en[1],
57*4882a593Smuzhiyun ps->gpe0_en[2], ps->gpe0_en[3]);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun debug("GEN_PMCON: %04x %04x %04x\n",
60*4882a593Smuzhiyun ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun debug("Previous Sleep State: S%d\n",
63*4882a593Smuzhiyun ps->prev_sleep_state);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Fill power state structure from ACPI PM registers */
power_state_get(struct udevice * pch_dev,struct chipset_power_state * ps)67*4882a593Smuzhiyun void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
70*4882a593Smuzhiyun ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
71*4882a593Smuzhiyun ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
72*4882a593Smuzhiyun ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS);
73*4882a593Smuzhiyun ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS);
74*4882a593Smuzhiyun ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
75*4882a593Smuzhiyun ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
76*4882a593Smuzhiyun ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));
77*4882a593Smuzhiyun ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3));
78*4882a593Smuzhiyun ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
79*4882a593Smuzhiyun ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1));
80*4882a593Smuzhiyun ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));
81*4882a593Smuzhiyun ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun dm_pci_read_config16(pch_dev, GEN_PMCON_1, &ps->gen_pmcon1);
84*4882a593Smuzhiyun dm_pci_read_config16(pch_dev, GEN_PMCON_2, &ps->gen_pmcon2);
85*4882a593Smuzhiyun dm_pci_read_config16(pch_dev, GEN_PMCON_3, &ps->gen_pmcon3);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun ps->prev_sleep_state = prev_sleep_state(ps);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun dump_power_state(ps);
90*4882a593Smuzhiyun }
91