1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2011 The Chromium Authors
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/arch/iomap.h>
11*4882a593Smuzhiyun #include <asm/arch/pch.h>
12*4882a593Smuzhiyun
broadwell_northbridge_early_init(struct udevice * dev)13*4882a593Smuzhiyun static int broadwell_northbridge_early_init(struct udevice *dev)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun /* Move earlier? */
16*4882a593Smuzhiyun dm_pci_write_config32(dev, PCIEXBAR + 4, 0);
17*4882a593Smuzhiyun /* 64MiB - 0-63 buses */
18*4882a593Smuzhiyun dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1);
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
21*4882a593Smuzhiyun dm_pci_write_config32(dev, DMIBAR, DMI_BASE_ADDRESS | 1);
22*4882a593Smuzhiyun dm_pci_write_config32(dev, EPBAR, EP_BASE_ADDRESS | 1);
23*4882a593Smuzhiyun writel(EDRAM_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + EDRAMBAR);
24*4882a593Smuzhiyun writel(GDXC_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + GDXCBAR);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Set C0000-FFFFF to access RAM on both reads and writes */
27*4882a593Smuzhiyun dm_pci_write_config8(dev, PAM0, 0x30);
28*4882a593Smuzhiyun dm_pci_write_config8(dev, PAM1, 0x33);
29*4882a593Smuzhiyun dm_pci_write_config8(dev, PAM2, 0x33);
30*4882a593Smuzhiyun dm_pci_write_config8(dev, PAM3, 0x33);
31*4882a593Smuzhiyun dm_pci_write_config8(dev, PAM4, 0x33);
32*4882a593Smuzhiyun dm_pci_write_config8(dev, PAM5, 0x33);
33*4882a593Smuzhiyun dm_pci_write_config8(dev, PAM6, 0x33);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Device enable: IGD and Mini-HD */
36*4882a593Smuzhiyun dm_pci_write_config32(dev, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun return 0;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
broadwell_northbridge_probe(struct udevice * dev)41*4882a593Smuzhiyun static int broadwell_northbridge_probe(struct udevice *dev)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun if (!(gd->flags & GD_FLG_RELOC))
44*4882a593Smuzhiyun return broadwell_northbridge_early_init(dev);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun return 0;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun static const struct udevice_id broadwell_northbridge_ids[] = {
50*4882a593Smuzhiyun { .compatible = "intel,broadwell-northbridge" },
51*4882a593Smuzhiyun { }
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun U_BOOT_DRIVER(broadwell_northbridge_drv) = {
55*4882a593Smuzhiyun .name = "broadwell_northbridge",
56*4882a593Smuzhiyun .id = UCLASS_NORTHBRIDGE,
57*4882a593Smuzhiyun .of_match = broadwell_northbridge_ids,
58*4882a593Smuzhiyun .probe = broadwell_northbridge_probe,
59*4882a593Smuzhiyun };
60