1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2016 Google, Inc
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Based on code from coreboot src/soc/intel/broadwell/me_status.c
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <errno.h>
11*4882a593Smuzhiyun #include <asm/arch/me.h>
12*4882a593Smuzhiyun
me_read_dword_ptr(struct udevice * dev,void * ptr,int offset)13*4882a593Smuzhiyun static inline void me_read_dword_ptr(struct udevice *dev, void *ptr, int offset)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun u32 dword;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun dm_pci_read_config32(dev, offset, &dword);
18*4882a593Smuzhiyun memcpy(ptr, &dword, sizeof(dword));
19*4882a593Smuzhiyun }
20*4882a593Smuzhiyun
intel_me_hsio_version(struct udevice * dev,uint16_t * versionp,uint16_t * checksump)21*4882a593Smuzhiyun int intel_me_hsio_version(struct udevice *dev, uint16_t *versionp,
22*4882a593Smuzhiyun uint16_t *checksump)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun int count;
25*4882a593Smuzhiyun u32 hsiover;
26*4882a593Smuzhiyun struct me_hfs hfs;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* Query for HSIO version, overloads H_GS and HFS */
29*4882a593Smuzhiyun dm_pci_write_config32(dev, PCI_ME_H_GS,
30*4882a593Smuzhiyun ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* Must wait for ME acknowledgement */
33*4882a593Smuzhiyun for (count = ME_RETRY; count > 0; --count) {
34*4882a593Smuzhiyun me_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
35*4882a593Smuzhiyun if (hfs.bios_msg_ack)
36*4882a593Smuzhiyun break;
37*4882a593Smuzhiyun udelay(ME_DELAY);
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun if (!count) {
40*4882a593Smuzhiyun debug("ERROR: ME failed to respond\n");
41*4882a593Smuzhiyun return -ETIMEDOUT;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* HSIO version should be in HFS_5 */
45*4882a593Smuzhiyun dm_pci_read_config32(dev, PCI_ME_HFS5, &hsiover);
46*4882a593Smuzhiyun *versionp = hsiover >> 16;
47*4882a593Smuzhiyun *checksump = hsiover & 0xffff;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun debug("ME: HSIO Version : %d (CRC 0x%04x)\n",
50*4882a593Smuzhiyun *versionp, *checksump);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* Reset registers to normal behavior */
53*4882a593Smuzhiyun dm_pci_write_config32(dev, PCI_ME_H_GS,
54*4882a593Smuzhiyun ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return 0;
57*4882a593Smuzhiyun }
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