1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2016 Google, Inc
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Modified from coreboot
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <errno.h>
11*4882a593Smuzhiyun #include <asm/intel_regs.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <asm/arch/pch.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define IOBP_RETRY 1000
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* IO Buffer Programming */
18*4882a593Smuzhiyun #define IOBPIRI 0x2330
19*4882a593Smuzhiyun #define IOBPD 0x2334
20*4882a593Smuzhiyun #define IOBPS 0x2338
21*4882a593Smuzhiyun #define IOBPS_READY 0x0001
22*4882a593Smuzhiyun #define IOBPS_TX_MASK 0x0006
23*4882a593Smuzhiyun #define IOBPS_MASK 0xff00
24*4882a593Smuzhiyun #define IOBPS_READ 0x0600
25*4882a593Smuzhiyun #define IOBPS_WRITE 0x0700
26*4882a593Smuzhiyun #define IOBPU 0x233a
27*4882a593Smuzhiyun #define IOBPU_MAGIC 0xf000
28*4882a593Smuzhiyun #define IOBP_PCICFG_READ 0x0400
29*4882a593Smuzhiyun #define IOBP_PCICFG_WRITE 0x0500
30*4882a593Smuzhiyun
iobp_poll(void)31*4882a593Smuzhiyun static inline int iobp_poll(void)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun unsigned try;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun for (try = IOBP_RETRY; try > 0; try--) {
36*4882a593Smuzhiyun u16 status = readw(RCB_REG(IOBPS));
37*4882a593Smuzhiyun if ((status & IOBPS_READY) == 0)
38*4882a593Smuzhiyun return 1;
39*4882a593Smuzhiyun udelay(10);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun printf("IOBP: timeout waiting for transaction to complete\n");
43*4882a593Smuzhiyun return 0;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
pch_iobp_trans_start(u32 address,int op)46*4882a593Smuzhiyun int pch_iobp_trans_start(u32 address, int op)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun if (!iobp_poll())
49*4882a593Smuzhiyun return 0;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* Set the address */
52*4882a593Smuzhiyun writel(address, RCB_REG(IOBPIRI));
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* READ OPCODE */
55*4882a593Smuzhiyun clrsetbits_le16(RCB_REG(IOBPS), IOBPS_MASK, op);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return 1;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
pch_iobp_trans_finish(void)60*4882a593Smuzhiyun int pch_iobp_trans_finish(void)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun u16 status;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* Undocumented magic */
65*4882a593Smuzhiyun writew(IOBPU_MAGIC, RCB_REG(IOBPU));
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* Set ready bit */
68*4882a593Smuzhiyun setbits_le16(RCB_REG(IOBPS), IOBPS_READY);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun if (!iobp_poll())
71*4882a593Smuzhiyun return 1;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* Check for successful transaction */
74*4882a593Smuzhiyun status = readw(RCB_REG(IOBPS));
75*4882a593Smuzhiyun if (status & IOBPS_TX_MASK)
76*4882a593Smuzhiyun return 1;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun return 0;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
pch_iobp_read(u32 address)81*4882a593Smuzhiyun u32 pch_iobp_read(u32 address)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun if (!pch_iobp_trans_start(address, IOBPS_READ))
84*4882a593Smuzhiyun return 0;
85*4882a593Smuzhiyun if (pch_iobp_trans_finish()) {
86*4882a593Smuzhiyun printf("IOBP: read 0x%08x failed\n", address);
87*4882a593Smuzhiyun return 0;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* Read IOBP data */
91*4882a593Smuzhiyun return readl(RCB_REG(IOBPD));
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
pch_iobp_write(u32 address,u32 data)94*4882a593Smuzhiyun int pch_iobp_write(u32 address, u32 data)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun if (!pch_iobp_trans_start(address, IOBPS_WRITE))
97*4882a593Smuzhiyun return -EIO;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun writel(data, RCB_REG(IOBPD));
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun if (pch_iobp_trans_finish()) {
102*4882a593Smuzhiyun printf("IOBP: write 0x%08x failed\n", address);
103*4882a593Smuzhiyun return -EIO;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun return 0;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
pch_iobp_update(u32 address,u32 andvalue,u32 orvalue)109*4882a593Smuzhiyun int pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun u32 data = pch_iobp_read(address);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* Update the data */
114*4882a593Smuzhiyun data &= andvalue;
115*4882a593Smuzhiyun data |= orvalue;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun return pch_iobp_write(address, data);
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
pch_iobp_exec(u32 addr,u16 op_code,u8 route_id,u32 * data,u8 * resp)120*4882a593Smuzhiyun int pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun if (!data || !resp)
123*4882a593Smuzhiyun return 0;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun *resp = -1;
126*4882a593Smuzhiyun if (!iobp_poll())
127*4882a593Smuzhiyun return -EIO;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun writel(addr, RCB_REG(IOBPIRI));
130*4882a593Smuzhiyun clrsetbits_le16(RCB_REG(IOBPS), 0xff00, op_code);
131*4882a593Smuzhiyun writew(IOBPU_MAGIC | route_id, RCB_REG(IOBPU));
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun writel(*data, RCB_REG(IOBPD));
134*4882a593Smuzhiyun /* Set IOBPS[0] to trigger IOBP transaction*/
135*4882a593Smuzhiyun setbits_le16(RCB_REG(IOBPS), 1);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun if (!iobp_poll())
138*4882a593Smuzhiyun return -EIO;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun *resp = (readw(RCB_REG(IOBPS)) & IOBPS_TX_MASK) >> 1;
141*4882a593Smuzhiyun *data = readl(RCB_REG(IOBPD));
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun return 0;
144*4882a593Smuzhiyun }
145