xref: /OK3568_Linux_fs/u-boot/arch/x86/cpu/baytrail/fsp_configs.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2013, Intel Corporation
3*4882a593Smuzhiyun  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4*4882a593Smuzhiyun  * Copyright (C) 2015, Kodak Alaris, Inc
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * SPDX-License-Identifier:	Intel
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <fdtdec.h>
11*4882a593Smuzhiyun #include <asm/arch/fsp/azalia.h>
12*4882a593Smuzhiyun #include <asm/fsp/fsp_support.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun /* ALC262 Verb Table - 10EC0262 */
17*4882a593Smuzhiyun static const uint32_t verb_table_data13[] = {
18*4882a593Smuzhiyun 	/* Pin Complex (NID 0x11) */
19*4882a593Smuzhiyun 	0x01171cf0,
20*4882a593Smuzhiyun 	0x01171d11,
21*4882a593Smuzhiyun 	0x01171e11,
22*4882a593Smuzhiyun 	0x01171f41,
23*4882a593Smuzhiyun 	/* Pin Complex (NID 0x12) */
24*4882a593Smuzhiyun 	0x01271cf0,
25*4882a593Smuzhiyun 	0x01271d11,
26*4882a593Smuzhiyun 	0x01271e11,
27*4882a593Smuzhiyun 	0x01271f41,
28*4882a593Smuzhiyun 	/* Pin Complex (NID 0x14) */
29*4882a593Smuzhiyun 	0x01471c10,
30*4882a593Smuzhiyun 	0x01471d40,
31*4882a593Smuzhiyun 	0x01471e01,
32*4882a593Smuzhiyun 	0x01471f01,
33*4882a593Smuzhiyun 	/* Pin Complex (NID 0x15) */
34*4882a593Smuzhiyun 	0x01571cf0,
35*4882a593Smuzhiyun 	0x01571d11,
36*4882a593Smuzhiyun 	0x01571e11,
37*4882a593Smuzhiyun 	0x01571f41,
38*4882a593Smuzhiyun 	/* Pin Complex (NID 0x16) */
39*4882a593Smuzhiyun 	0x01671cf0,
40*4882a593Smuzhiyun 	0x01671d11,
41*4882a593Smuzhiyun 	0x01671e11,
42*4882a593Smuzhiyun 	0x01671f41,
43*4882a593Smuzhiyun 	/* Pin Complex (NID 0x18) */
44*4882a593Smuzhiyun 	0x01871c20,
45*4882a593Smuzhiyun 	0x01871d98,
46*4882a593Smuzhiyun 	0x01871ea1,
47*4882a593Smuzhiyun 	0x01871f01,
48*4882a593Smuzhiyun 	/* Pin Complex (NID 0x19) */
49*4882a593Smuzhiyun 	0x01971c21,
50*4882a593Smuzhiyun 	0x01971d98,
51*4882a593Smuzhiyun 	0x01971ea1,
52*4882a593Smuzhiyun 	0x01971f02,
53*4882a593Smuzhiyun 	/* Pin Complex (NID 0x1A) */
54*4882a593Smuzhiyun 	0x01a71c2f,
55*4882a593Smuzhiyun 	0x01a71d30,
56*4882a593Smuzhiyun 	0x01a71e81,
57*4882a593Smuzhiyun 	0x01a71f01,
58*4882a593Smuzhiyun 	/* Pin Complex */
59*4882a593Smuzhiyun 	0x01b71c1f,
60*4882a593Smuzhiyun 	0x01b71d40,
61*4882a593Smuzhiyun 	0x01b71e21,
62*4882a593Smuzhiyun 	0x01b71f02,
63*4882a593Smuzhiyun 	/* Pin Complex */
64*4882a593Smuzhiyun 	0x01c71cf0,
65*4882a593Smuzhiyun 	0x01c71d11,
66*4882a593Smuzhiyun 	0x01c71e11,
67*4882a593Smuzhiyun 	0x01c71f41,
68*4882a593Smuzhiyun 	/* Pin Complex */
69*4882a593Smuzhiyun 	0x01d71c01,
70*4882a593Smuzhiyun 	0x01d71dc6,
71*4882a593Smuzhiyun 	0x01d71e14,
72*4882a593Smuzhiyun 	0x01d71f40,
73*4882a593Smuzhiyun 	/* Pin Complex */
74*4882a593Smuzhiyun 	0x01e71cf0,
75*4882a593Smuzhiyun 	0x01e71d11,
76*4882a593Smuzhiyun 	0x01e71e11,
77*4882a593Smuzhiyun 	0x01e71f41,
78*4882a593Smuzhiyun 	/* Pin Complex */
79*4882a593Smuzhiyun 	0x01f71cf0,
80*4882a593Smuzhiyun 	0x01f71d11,
81*4882a593Smuzhiyun 	0x01f71e11,
82*4882a593Smuzhiyun 	0x01f71f41,
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun /*
86*4882a593Smuzhiyun  * This needs to be in ROM since if we put it in CAR, FSP init loses it when
87*4882a593Smuzhiyun  * it drops CAR.
88*4882a593Smuzhiyun  *
89*4882a593Smuzhiyun  * TODO(sjg@chromium.org): Move to device tree when FSP allows it
90*4882a593Smuzhiyun  *
91*4882a593Smuzhiyun  * VerbTable: (RealTek ALC262)
92*4882a593Smuzhiyun  * Revision ID = 0xFF, support all steps
93*4882a593Smuzhiyun  * Codec Verb Table For AZALIA
94*4882a593Smuzhiyun  * Codec Address: CAd value (0/1/2)
95*4882a593Smuzhiyun  * Codec Vendor: 0x10EC0262
96*4882a593Smuzhiyun  */
97*4882a593Smuzhiyun static const struct pch_azalia_verb_table azalia_verb_table[] = {
98*4882a593Smuzhiyun 	{
99*4882a593Smuzhiyun 		{
100*4882a593Smuzhiyun 			0x10ec0262,
101*4882a593Smuzhiyun 			0x0000,
102*4882a593Smuzhiyun 			0xff,
103*4882a593Smuzhiyun 			0x01,
104*4882a593Smuzhiyun 			0x000b,
105*4882a593Smuzhiyun 			0x0002,
106*4882a593Smuzhiyun 		},
107*4882a593Smuzhiyun 		verb_table_data13
108*4882a593Smuzhiyun 	}
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun const struct pch_azalia_config azalia_config = {
112*4882a593Smuzhiyun 	.pme_enable = 1,
113*4882a593Smuzhiyun 	.docking_supported = 1,
114*4882a593Smuzhiyun 	.docking_attached = 0,
115*4882a593Smuzhiyun 	.hdmi_codec_enable = 1,
116*4882a593Smuzhiyun 	.azalia_v_ci_enable = 1,
117*4882a593Smuzhiyun 	.rsvdbits = 0,
118*4882a593Smuzhiyun 	.azalia_verb_table_num = 1,
119*4882a593Smuzhiyun 	.azalia_verb_table = azalia_verb_table,
120*4882a593Smuzhiyun 	.reset_wait_timer_us = 300
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun /**
124*4882a593Smuzhiyun  * Override the FSP's configuration data.
125*4882a593Smuzhiyun  * If the device tree does not specify an integer setting, use the default
126*4882a593Smuzhiyun  * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file.
127*4882a593Smuzhiyun  */
update_fsp_configs(struct fsp_config_data * config,struct fspinit_rtbuf * rt_buf)128*4882a593Smuzhiyun void update_fsp_configs(struct fsp_config_data *config,
129*4882a593Smuzhiyun 			struct fspinit_rtbuf *rt_buf)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun 	struct upd_region *fsp_upd = &config->fsp_upd;
132*4882a593Smuzhiyun 	struct memory_down_data *mem;
133*4882a593Smuzhiyun 	const void *blob = gd->fdt_blob;
134*4882a593Smuzhiyun 	int node;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	/* Initialize runtime buffer for fsp_init() */
137*4882a593Smuzhiyun 	rt_buf->common.stack_top = config->common.stack_top - 32;
138*4882a593Smuzhiyun 	rt_buf->common.boot_mode = config->common.boot_mode;
139*4882a593Smuzhiyun 	rt_buf->common.upd_data = &config->fsp_upd;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP);
144*4882a593Smuzhiyun 	if (node < 0) {
145*4882a593Smuzhiyun 		debug("%s: Cannot find FSP node\n", __func__);
146*4882a593Smuzhiyun 		return;
147*4882a593Smuzhiyun 	}
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	fsp_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node,
150*4882a593Smuzhiyun 						     "fsp,mrc-init-tseg-size",
151*4882a593Smuzhiyun 						     MRC_INIT_TSEG_SIZE_1MB);
152*4882a593Smuzhiyun 	fsp_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node,
153*4882a593Smuzhiyun 						     "fsp,mrc-init-mmio-size",
154*4882a593Smuzhiyun 						     MRC_INIT_MMIO_SIZE_2048MB);
155*4882a593Smuzhiyun 	fsp_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node,
156*4882a593Smuzhiyun 						     "fsp,mrc-init-spd-addr1",
157*4882a593Smuzhiyun 						     0xa0);
158*4882a593Smuzhiyun 	fsp_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node,
159*4882a593Smuzhiyun 						     "fsp,mrc-init-spd-addr2",
160*4882a593Smuzhiyun 						     0xa2);
161*4882a593Smuzhiyun 	fsp_upd->emmc_boot_mode = fdtdec_get_int(blob, node,
162*4882a593Smuzhiyun 						 "fsp,emmc-boot-mode",
163*4882a593Smuzhiyun 						 EMMC_BOOT_MODE_EMMC41);
164*4882a593Smuzhiyun 	fsp_upd->enable_sdio = fdtdec_get_bool(blob, node, "fsp,enable-sdio");
165*4882a593Smuzhiyun 	fsp_upd->enable_sdcard = fdtdec_get_bool(blob, node,
166*4882a593Smuzhiyun 						 "fsp,enable-sdcard");
167*4882a593Smuzhiyun 	fsp_upd->enable_hsuart0 = fdtdec_get_bool(blob, node,
168*4882a593Smuzhiyun 						  "fsp,enable-hsuart0");
169*4882a593Smuzhiyun 	fsp_upd->enable_hsuart1 = fdtdec_get_bool(blob, node,
170*4882a593Smuzhiyun 						  "fsp,enable-hsuart1");
171*4882a593Smuzhiyun 	fsp_upd->enable_spi = fdtdec_get_bool(blob, node, "fsp,enable-spi");
172*4882a593Smuzhiyun 	fsp_upd->enable_sata = fdtdec_get_bool(blob, node, "fsp,enable-sata");
173*4882a593Smuzhiyun 	fsp_upd->sata_mode = fdtdec_get_int(blob, node, "fsp,sata-mode",
174*4882a593Smuzhiyun 					    SATA_MODE_AHCI);
175*4882a593Smuzhiyun 	fsp_upd->enable_azalia = fdtdec_get_bool(blob, node,
176*4882a593Smuzhiyun 						 "fsp,enable-azalia");
177*4882a593Smuzhiyun 	fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci");
178*4882a593Smuzhiyun 	fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode",
179*4882a593Smuzhiyun 					   LPE_MODE_PCI);
180*4882a593Smuzhiyun 	fsp_upd->lpss_sio_mode = fdtdec_get_int(blob, node, "fsp,lpss-sio-mode",
181*4882a593Smuzhiyun 					   LPSS_SIO_MODE_PCI);
182*4882a593Smuzhiyun 	fsp_upd->enable_dma0 = fdtdec_get_bool(blob, node, "fsp,enable-dma0");
183*4882a593Smuzhiyun 	fsp_upd->enable_dma1 = fdtdec_get_bool(blob, node, "fsp,enable-dma1");
184*4882a593Smuzhiyun 	fsp_upd->enable_i2_c0 = fdtdec_get_bool(blob, node, "fsp,enable-i2c0");
185*4882a593Smuzhiyun 	fsp_upd->enable_i2_c1 = fdtdec_get_bool(blob, node, "fsp,enable-i2c1");
186*4882a593Smuzhiyun 	fsp_upd->enable_i2_c2 = fdtdec_get_bool(blob, node, "fsp,enable-i2c2");
187*4882a593Smuzhiyun 	fsp_upd->enable_i2_c3 = fdtdec_get_bool(blob, node, "fsp,enable-i2c3");
188*4882a593Smuzhiyun 	fsp_upd->enable_i2_c4 = fdtdec_get_bool(blob, node, "fsp,enable-i2c4");
189*4882a593Smuzhiyun 	fsp_upd->enable_i2_c5 = fdtdec_get_bool(blob, node, "fsp,enable-i2c5");
190*4882a593Smuzhiyun 	fsp_upd->enable_i2_c6 = fdtdec_get_bool(blob, node, "fsp,enable-i2c6");
191*4882a593Smuzhiyun 	fsp_upd->enable_pwm0 = fdtdec_get_bool(blob, node, "fsp,enable-pwm0");
192*4882a593Smuzhiyun 	fsp_upd->enable_pwm1 = fdtdec_get_bool(blob, node, "fsp,enable-pwm1");
193*4882a593Smuzhiyun 	fsp_upd->enable_hsi = fdtdec_get_bool(blob, node, "fsp,enable-hsi");
194*4882a593Smuzhiyun 	fsp_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node,
195*4882a593Smuzhiyun 			"fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_64MB);
196*4882a593Smuzhiyun 	fsp_upd->aperture_size = fdtdec_get_int(blob, node, "fsp,aperture-size",
197*4882a593Smuzhiyun 						APERTURE_SIZE_256MB);
198*4882a593Smuzhiyun 	fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size",
199*4882a593Smuzhiyun 					   GTT_SIZE_2MB);
200*4882a593Smuzhiyun 	fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node,
201*4882a593Smuzhiyun 						 "fsp,mrc-debug-msg");
202*4882a593Smuzhiyun 	fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable");
203*4882a593Smuzhiyun 	fsp_upd->scc_mode = fdtdec_get_int(blob, node, "fsp,scc-mode",
204*4882a593Smuzhiyun 					   SCC_MODE_PCI);
205*4882a593Smuzhiyun 	fsp_upd->igd_render_standby = fdtdec_get_bool(blob, node,
206*4882a593Smuzhiyun 						      "fsp,igd-render-standby");
207*4882a593Smuzhiyun 	fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node,
208*4882a593Smuzhiyun 						  "fsp,txe-uma-enable");
209*4882a593Smuzhiyun 	fsp_upd->os_selection = fdtdec_get_int(blob, node, "fsp,os-selection",
210*4882a593Smuzhiyun 					       OS_SELECTION_LINUX);
211*4882a593Smuzhiyun 	fsp_upd->emmc45_ddr50_enabled = fdtdec_get_bool(blob, node,
212*4882a593Smuzhiyun 			"fsp,emmc45-ddr50-enabled");
213*4882a593Smuzhiyun 	fsp_upd->emmc45_hs200_enabled = fdtdec_get_bool(blob, node,
214*4882a593Smuzhiyun 			"fsp,emmc45-hs200-enabled");
215*4882a593Smuzhiyun 	fsp_upd->emmc45_retune_timer_value = fdtdec_get_int(blob, node,
216*4882a593Smuzhiyun 			"fsp,emmc45-retune-timer-value", 8);
217*4882a593Smuzhiyun 	fsp_upd->enable_igd = fdtdec_get_bool(blob, node, "fsp,enable-igd");
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	mem = &fsp_upd->memory_params;
220*4882a593Smuzhiyun 	mem->enable_memory_down = fdtdec_get_bool(blob, node,
221*4882a593Smuzhiyun 						  "fsp,enable-memory-down");
222*4882a593Smuzhiyun 	if (mem->enable_memory_down) {
223*4882a593Smuzhiyun 		node = fdtdec_next_compatible(blob, node,
224*4882a593Smuzhiyun 					      COMPAT_INTEL_BAYTRAIL_FSP_MDP);
225*4882a593Smuzhiyun 		if (node < 0) {
226*4882a593Smuzhiyun 			debug("%s: Cannot find FSP memory-down-params node\n",
227*4882a593Smuzhiyun 			      __func__);
228*4882a593Smuzhiyun 		} else {
229*4882a593Smuzhiyun 			mem->dram_speed = fdtdec_get_int(blob, node,
230*4882a593Smuzhiyun 							 "fsp,dram-speed",
231*4882a593Smuzhiyun 							 DRAM_SPEED_1333MTS);
232*4882a593Smuzhiyun 			mem->dram_type = fdtdec_get_int(blob, node,
233*4882a593Smuzhiyun 							"fsp,dram-type",
234*4882a593Smuzhiyun 							DRAM_TYPE_DDR3L);
235*4882a593Smuzhiyun 			mem->dimm_0_enable = fdtdec_get_bool(blob, node,
236*4882a593Smuzhiyun 					"fsp,dimm-0-enable");
237*4882a593Smuzhiyun 			mem->dimm_1_enable = fdtdec_get_bool(blob, node,
238*4882a593Smuzhiyun 					"fsp,dimm-1-enable");
239*4882a593Smuzhiyun 			mem->dimm_width = fdtdec_get_int(blob, node,
240*4882a593Smuzhiyun 							 "fsp,dimm-width",
241*4882a593Smuzhiyun 							 DIMM_WIDTH_X8);
242*4882a593Smuzhiyun 			mem->dimm_density = fdtdec_get_int(blob, node,
243*4882a593Smuzhiyun 							   "fsp,dimm-density",
244*4882a593Smuzhiyun 							   DIMM_DENSITY_2GBIT);
245*4882a593Smuzhiyun 			mem->dimm_bus_width = fdtdec_get_int(blob, node,
246*4882a593Smuzhiyun 					"fsp,dimm-bus-width",
247*4882a593Smuzhiyun 					DIMM_BUS_WIDTH_64BITS);
248*4882a593Smuzhiyun 			mem->dimm_sides = fdtdec_get_int(blob, node,
249*4882a593Smuzhiyun 							 "fsp,dimm-sides",
250*4882a593Smuzhiyun 							 DIMM_SIDES_1RANKS);
251*4882a593Smuzhiyun 			mem->dimm_tcl = fdtdec_get_int(blob, node,
252*4882a593Smuzhiyun 						       "fsp,dimm-tcl", 0x09);
253*4882a593Smuzhiyun 			mem->dimm_trpt_rcd = fdtdec_get_int(blob, node,
254*4882a593Smuzhiyun 					"fsp,dimm-trpt-rcd", 0x09);
255*4882a593Smuzhiyun 			mem->dimm_twr = fdtdec_get_int(blob, node,
256*4882a593Smuzhiyun 						       "fsp,dimm-twr", 0x0a);
257*4882a593Smuzhiyun 			mem->dimm_twtr = fdtdec_get_int(blob, node,
258*4882a593Smuzhiyun 							"fsp,dimm-twtr", 0x05);
259*4882a593Smuzhiyun 			mem->dimm_trrd = fdtdec_get_int(blob, node,
260*4882a593Smuzhiyun 							"fsp,dimm-trrd", 0x04);
261*4882a593Smuzhiyun 			mem->dimm_trtp = fdtdec_get_int(blob, node,
262*4882a593Smuzhiyun 							"fsp,dimm-trtp", 0x05);
263*4882a593Smuzhiyun 			mem->dimm_tfaw = fdtdec_get_int(blob, node,
264*4882a593Smuzhiyun 							"fsp,dimm-tfaw", 0x14);
265*4882a593Smuzhiyun 		}
266*4882a593Smuzhiyun 	}
267*4882a593Smuzhiyun }
268