1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015 Google, Inc
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <errno.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define PCI_DEV_CONFIG(segbus, dev, fn) ( \
12*4882a593Smuzhiyun (((segbus) & 0xfff) << 20) | \
13*4882a593Smuzhiyun (((dev) & 0x1f) << 15) | \
14*4882a593Smuzhiyun (((fn) & 0x07) << 12))
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /* Platform Controller Unit */
17*4882a593Smuzhiyun #define LPC_DEV 0x1f
18*4882a593Smuzhiyun #define LPC_FUNC 0
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* Enable UART */
21*4882a593Smuzhiyun #define UART_CONT 0x80
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* SCORE Pad definitions */
24*4882a593Smuzhiyun #define UART_RXD_PAD 82
25*4882a593Smuzhiyun #define UART_TXD_PAD 83
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Pad base: PAD_CONF0[n]= PAD_BASE + 16 * n */
28*4882a593Smuzhiyun #define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE)
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* IO Memory */
31*4882a593Smuzhiyun #define IO_BASE_ADDRESS 0xfed0c000
32*4882a593Smuzhiyun #define IO_BASE_OFFSET_GPSCORE 0x0000
33*4882a593Smuzhiyun #define IO_BASE_OFFSET_GPNCORE 0x1000
34*4882a593Smuzhiyun #define IO_BASE_OFFSET_GPSSUS 0x2000
35*4882a593Smuzhiyun #define IO_BASE_SIZE 0x4000
36*4882a593Smuzhiyun
score_pconf0(int pad_num)37*4882a593Smuzhiyun static inline unsigned int score_pconf0(int pad_num)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun return GPSCORE_PAD_BASE + pad_num * 16;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
score_select_func(int pad,int func)42*4882a593Smuzhiyun static void score_select_func(int pad, int func)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun uint32_t reg;
45*4882a593Smuzhiyun uint32_t pconf0_addr = score_pconf0(pad);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun reg = readl(pconf0_addr);
48*4882a593Smuzhiyun reg &= ~0x7;
49*4882a593Smuzhiyun reg |= func & 0x7;
50*4882a593Smuzhiyun writel(reg, pconf0_addr);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
x86_pci_write_config32(int dev,unsigned int where,u32 value)53*4882a593Smuzhiyun static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun unsigned long addr;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
58*4882a593Smuzhiyun writel(value, addr);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* This can be called after memory-mapped PCI is working */
setup_internal_uart(int enable)62*4882a593Smuzhiyun int setup_internal_uart(int enable)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun /* Enable or disable the legacy UART hardware */
65*4882a593Smuzhiyun x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
66*4882a593Smuzhiyun enable);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* All done for the disable part, so just return */
69*4882a593Smuzhiyun if (!enable)
70*4882a593Smuzhiyun return 0;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /*
73*4882a593Smuzhiyun * Set up the pads to the UART function. This allows the signals to
74*4882a593Smuzhiyun * leave the chip
75*4882a593Smuzhiyun */
76*4882a593Smuzhiyun score_select_func(UART_RXD_PAD, 1);
77*4882a593Smuzhiyun score_select_func(UART_TXD_PAD, 1);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* TODO(sjg@chromium.org): Call debug_uart_init() */
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return 0;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
board_debug_uart_init(void)84*4882a593Smuzhiyun void board_debug_uart_init(void)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun setup_internal_uart(1);
87*4882a593Smuzhiyun }
88