1*4882a593Smuzhiyun #ifndef _ASM_CPU_SH7780_H_ 2*4882a593Smuzhiyun #define _ASM_CPU_SH7780_H_ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * Copyright (c) 2007,2008 Nobuhiro Iwamatsu 6*4882a593Smuzhiyun * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CACHE_OC_NUM_WAYS 1 12*4882a593Smuzhiyun #define CCR_CACHE_INIT 0x0000090b 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Exceptions */ 15*4882a593Smuzhiyun #define TRA 0xFF000020 16*4882a593Smuzhiyun #define EXPEVT 0xFF000024 17*4882a593Smuzhiyun #define INTEVT 0xFF000028 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Memory Management Unit */ 20*4882a593Smuzhiyun #define PTEH 0xFF000000 21*4882a593Smuzhiyun #define PTEL 0xFF000004 22*4882a593Smuzhiyun #define TTB 0xFF000008 23*4882a593Smuzhiyun #define TEA 0xFF00000C 24*4882a593Smuzhiyun #define MMUCR 0xFF000010 25*4882a593Smuzhiyun #define PASCR 0xFF000070 26*4882a593Smuzhiyun #define IRMCR 0xFF000078 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Cache Controller */ 29*4882a593Smuzhiyun #define CCR 0xFF00001C 30*4882a593Smuzhiyun #define QACR0 0xFF000038 31*4882a593Smuzhiyun #define QACR1 0xFF00003C 32*4882a593Smuzhiyun #define RAMCR 0xFF000074 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* L Memory */ 35*4882a593Smuzhiyun #define RAMCR 0xFF000074 36*4882a593Smuzhiyun #define LSA0 0xFF000050 37*4882a593Smuzhiyun #define LSA1 0xFF000054 38*4882a593Smuzhiyun #define LDA0 0xFF000058 39*4882a593Smuzhiyun #define LDA1 0xFF00005C 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Interrupt Controller */ 42*4882a593Smuzhiyun #define ICR0 0xFFD00000 43*4882a593Smuzhiyun #define ICR1 0xFFD0001C 44*4882a593Smuzhiyun #define INTPRI 0xFFD00010 45*4882a593Smuzhiyun #define INTREQ 0xFFD00024 46*4882a593Smuzhiyun #define INTMSK0 0xFFD00044 47*4882a593Smuzhiyun #define INTMSK1 0xFFD00048 48*4882a593Smuzhiyun #define INTMSK2 0xFFD40080 49*4882a593Smuzhiyun #define INTMSKCLR0 0xFFD00064 50*4882a593Smuzhiyun #define INTMSKCLR1 0xFFD00068 51*4882a593Smuzhiyun #define INTMSKCLR2 0xFFD40084 52*4882a593Smuzhiyun #define NMIFCR 0xFFD000C0 53*4882a593Smuzhiyun #define USERIMASK 0xFFD30000 54*4882a593Smuzhiyun #define INT2PRI0 0xFFD40000 55*4882a593Smuzhiyun #define INT2PRI1 0xFFD40004 56*4882a593Smuzhiyun #define INT2PRI2 0xFFD40008 57*4882a593Smuzhiyun #define INT2PRI3 0xFFD4000C 58*4882a593Smuzhiyun #define INT2PRI4 0xFFD40010 59*4882a593Smuzhiyun #define INT2PRI5 0xFFD40014 60*4882a593Smuzhiyun #define INT2PRI6 0xFFD40018 61*4882a593Smuzhiyun #define INT2PRI7 0xFFD4001C 62*4882a593Smuzhiyun #define INT2A0 0xFFD40030 63*4882a593Smuzhiyun #define INT2A1 0xFFD40034 64*4882a593Smuzhiyun #define INT2MSKR 0xFFD40038 65*4882a593Smuzhiyun #define INT2MSKCR 0xFFD4003C 66*4882a593Smuzhiyun #define INT2B0 0xFFD40040 67*4882a593Smuzhiyun #define INT2B1 0xFFD40044 68*4882a593Smuzhiyun #define INT2B2 0xFFD40048 69*4882a593Smuzhiyun #define INT2B3 0xFFD4004C 70*4882a593Smuzhiyun #define INT2B4 0xFFD40050 71*4882a593Smuzhiyun #define INT2B5 0xFFD40054 72*4882a593Smuzhiyun #define INT2B6 0xFFD40058 73*4882a593Smuzhiyun #define INT2B7 0xFFD4005C 74*4882a593Smuzhiyun #define INT2GPIC 0xFFD40090 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* local Bus State Controller */ 77*4882a593Smuzhiyun #define MMSELR 0xFF400020 78*4882a593Smuzhiyun #define BCR 0xFF801000 79*4882a593Smuzhiyun #define CS0BCR 0xFF802000 80*4882a593Smuzhiyun #define CS1BCR 0xFF802010 81*4882a593Smuzhiyun #define CS2BCR 0xFF802020 82*4882a593Smuzhiyun #define CS4BCR 0xFF802040 83*4882a593Smuzhiyun #define CS5BCR 0xFF802050 84*4882a593Smuzhiyun #define CS6BCR 0xFF802060 85*4882a593Smuzhiyun #define CS0WCR 0xFF802008 86*4882a593Smuzhiyun #define CS1WCR 0xFF802018 87*4882a593Smuzhiyun #define CS2WCR 0xFF802028 88*4882a593Smuzhiyun #define CS4WCR 0xFF802048 89*4882a593Smuzhiyun #define CS5WCR 0xFF802058 90*4882a593Smuzhiyun #define CS6WCR 0xFF802068 91*4882a593Smuzhiyun #define CS5PCR 0xFF802070 92*4882a593Smuzhiyun #define CS6PCR 0xFF802080 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* DDR-SDRAM I/F */ 95*4882a593Smuzhiyun #define MIM_1 0xFE800008 96*4882a593Smuzhiyun #define MIM_2 0xFE80000C 97*4882a593Smuzhiyun #define SCR_1 0xFE800010 98*4882a593Smuzhiyun #define SCR_2 0xFE800014 99*4882a593Smuzhiyun #define STR_1 0xFE800018 100*4882a593Smuzhiyun #define STR_2 0xFE80001C 101*4882a593Smuzhiyun #define SDR_1 0xFE800030 102*4882a593Smuzhiyun #define SDR_2 0xFE800034 103*4882a593Smuzhiyun #define DBK_1 0xFE800400 104*4882a593Smuzhiyun #define DBK_2 0xFE800404 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* PCI Controller */ 107*4882a593Smuzhiyun #define SH7780_PCIECR 0xFE000008 108*4882a593Smuzhiyun #define SH7780_PCIVID 0xFE040000 109*4882a593Smuzhiyun #define SH7780_PCIDID 0xFE040002 110*4882a593Smuzhiyun #define SH7780_PCICMD 0xFE040004 111*4882a593Smuzhiyun #define SH7780_PCISTATUS 0xFE040006 112*4882a593Smuzhiyun #define SH7780_PCIRID 0xFE040008 113*4882a593Smuzhiyun #define SH7780_PCIPIF 0xFE040009 114*4882a593Smuzhiyun #define SH7780_PCISUB 0xFE04000A 115*4882a593Smuzhiyun #define SH7780_PCIBCC 0xFE04000B 116*4882a593Smuzhiyun #define SH7780_PCICLS 0xFE04000C 117*4882a593Smuzhiyun #define SH7780_PCILTM 0xFE04000D 118*4882a593Smuzhiyun #define SH7780_PCIHDR 0xFE04000E 119*4882a593Smuzhiyun #define SH7780_PCIBIST 0xFE04000F 120*4882a593Smuzhiyun #define SH7780_PCIIBAR 0xFE040010 121*4882a593Smuzhiyun #define SH7780_PCIMBAR0 0xFE040014 122*4882a593Smuzhiyun #define SH7780_PCIMBAR1 0xFE040018 123*4882a593Smuzhiyun #define SH7780_PCISVID 0xFE04002C 124*4882a593Smuzhiyun #define SH7780_PCISID 0xFE04002E 125*4882a593Smuzhiyun #define SH7780_PCICP 0xFE040034 126*4882a593Smuzhiyun #define SH7780_PCIINTLINE 0xFE04003C 127*4882a593Smuzhiyun #define SH7780_PCIINTPIN 0xFE04003D 128*4882a593Smuzhiyun #define SH7780_PCIMINGNT 0xFE04003E 129*4882a593Smuzhiyun #define SH7780_PCIMAXLAT 0xFE04003F 130*4882a593Smuzhiyun #define SH7780_PCICID 0xFE040040 131*4882a593Smuzhiyun #define SH7780_PCINIP 0xFE040041 132*4882a593Smuzhiyun #define SH7780_PCIPMC 0xFE040042 133*4882a593Smuzhiyun #define SH7780_PCIPMCSR 0xFE040044 134*4882a593Smuzhiyun #define SH7780_PCIPMCSRBSE 0xFE040046 135*4882a593Smuzhiyun #define SH7780_PCI_CDD 0xFE040047 136*4882a593Smuzhiyun #define SH7780_PCICR 0xFE040100 137*4882a593Smuzhiyun #define SH7780_PCILSR0 0xFE040104 138*4882a593Smuzhiyun #define SH7780_PCILSR1 0xFE040108 139*4882a593Smuzhiyun #define SH7780_PCILAR0 0xFE04010C 140*4882a593Smuzhiyun #define SH7780_PCILAR1 0xFE040110 141*4882a593Smuzhiyun #define SH7780_PCIIR 0xFE040114 142*4882a593Smuzhiyun #define SH7780_PCIIMR 0xFE040118 143*4882a593Smuzhiyun #define SH7780_PCIAIR 0xFE04011C 144*4882a593Smuzhiyun #define SH7780_PCICIR 0xFE040120 145*4882a593Smuzhiyun #define SH7780_PCIAINT 0xFE040130 146*4882a593Smuzhiyun #define SH7780_PCIAINTM 0xFE040134 147*4882a593Smuzhiyun #define SH7780_PCIBMIR 0xFE040138 148*4882a593Smuzhiyun #define SH7780_PCIPAR 0xFE0401C0 149*4882a593Smuzhiyun #define SH7780_PCIPINT 0xFE0401CC 150*4882a593Smuzhiyun #define SH7780_PCIPINTM 0xFE0401D0 151*4882a593Smuzhiyun #define SH7780_PCIMBR0 0xFE0401E0 152*4882a593Smuzhiyun #define SH7780_PCIMBMR0 0xFE0401E4 153*4882a593Smuzhiyun #define SH7780_PCIMBR1 0xFE0401E8 154*4882a593Smuzhiyun #define SH7780_PCIMBMR1 0xFE0401EC 155*4882a593Smuzhiyun #define SH7780_PCIMBR2 0xFE0401F0 156*4882a593Smuzhiyun #define SH7780_PCIMBMR2 0xFE0401F4 157*4882a593Smuzhiyun #define SH7780_PCIIOBR 0xFE0401F8 158*4882a593Smuzhiyun #define SH7780_PCIIOBMR 0xFE0401FC 159*4882a593Smuzhiyun #define SH7780_PCICSCR0 0xFE040210 160*4882a593Smuzhiyun #define SH7780_PCICSCR1 0xFE040214 161*4882a593Smuzhiyun #define SH7780_PCICSAR0 0xFE040218 162*4882a593Smuzhiyun #define SH7780_PCICSAR1 0xFE04021C 163*4882a593Smuzhiyun #define SH7780_PCIPDR 0xFE040220 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun /* DMAC */ 166*4882a593Smuzhiyun #define DMAC_SAR0 0xFC808020 167*4882a593Smuzhiyun #define DMAC_DAR0 0xFC808024 168*4882a593Smuzhiyun #define DMAC_TCR0 0xFC808028 169*4882a593Smuzhiyun #define DMAC_CHCR0 0xFC80802C 170*4882a593Smuzhiyun #define DMAC_SAR1 0xFC808030 171*4882a593Smuzhiyun #define DMAC_DAR1 0xFC808034 172*4882a593Smuzhiyun #define DMAC_TCR1 0xFC808038 173*4882a593Smuzhiyun #define DMAC_CHCR1 0xFC80803C 174*4882a593Smuzhiyun #define DMAC_SAR2 0xFC808040 175*4882a593Smuzhiyun #define DMAC_DAR2 0xFC808044 176*4882a593Smuzhiyun #define DMAC_TCR2 0xFC808048 177*4882a593Smuzhiyun #define DMAC_CHCR2 0xFC80804C 178*4882a593Smuzhiyun #define DMAC_SAR3 0xFC808050 179*4882a593Smuzhiyun #define DMAC_DAR3 0xFC808054 180*4882a593Smuzhiyun #define DMAC_TCR3 0xFC808058 181*4882a593Smuzhiyun #define DMAC_CHCR3 0xFC80805C 182*4882a593Smuzhiyun #define DMAC_DMAOR0 0xFC808060 183*4882a593Smuzhiyun #define DMAC_SAR4 0xFC808070 184*4882a593Smuzhiyun #define DMAC_DAR4 0xFC808074 185*4882a593Smuzhiyun #define DMAC_TCR4 0xFC808078 186*4882a593Smuzhiyun #define DMAC_CHCR4 0xFC80807C 187*4882a593Smuzhiyun #define DMAC_SAR5 0xFC808080 188*4882a593Smuzhiyun #define DMAC_DAR5 0xFC808084 189*4882a593Smuzhiyun #define DMAC_TCR5 0xFC808088 190*4882a593Smuzhiyun #define DMAC_CHCR5 0xFC80808C 191*4882a593Smuzhiyun #define DMAC_SARB0 0xFC808120 192*4882a593Smuzhiyun #define DMAC_DARB0 0xFC808124 193*4882a593Smuzhiyun #define DMAC_TCRB0 0xFC808128 194*4882a593Smuzhiyun #define DMAC_SARB1 0xFC808130 195*4882a593Smuzhiyun #define DMAC_DARB1 0xFC808134 196*4882a593Smuzhiyun #define DMAC_TCRB1 0xFC808138 197*4882a593Smuzhiyun #define DMAC_SARB2 0xFC808140 198*4882a593Smuzhiyun #define DMAC_DARB2 0xFC808144 199*4882a593Smuzhiyun #define DMAC_TCRB2 0xFC808148 200*4882a593Smuzhiyun #define DMAC_SARB3 0xFC808150 201*4882a593Smuzhiyun #define DMAC_DARB3 0xFC808154 202*4882a593Smuzhiyun #define DMAC_TCRB3 0xFC808158 203*4882a593Smuzhiyun #define DMAC_DMARS0 0xFC809000 204*4882a593Smuzhiyun #define DMAC_DMARS1 0xFC809004 205*4882a593Smuzhiyun #define DMAC_DMARS2 0xFC809008 206*4882a593Smuzhiyun #define DMAC_SAR6 0xFC818020 207*4882a593Smuzhiyun #define DMAC_DAR6 0xFC818024 208*4882a593Smuzhiyun #define DMAC_TCR6 0xFC818028 209*4882a593Smuzhiyun #define DMAC_CHCR6 0xFC81802C 210*4882a593Smuzhiyun #define DMAC_SAR7 0xFC818030 211*4882a593Smuzhiyun #define DMAC_DAR7 0xFC818034 212*4882a593Smuzhiyun #define DMAC_TCR7 0xFC818038 213*4882a593Smuzhiyun #define DMAC_CHCR7 0xFC81803C 214*4882a593Smuzhiyun #define DMAC_SAR8 0xFC818040 215*4882a593Smuzhiyun #define DMAC_DAR8 0xFC818044 216*4882a593Smuzhiyun #define DMAC_TCR8 0xFC818048 217*4882a593Smuzhiyun #define DMAC_CHCR8 0xFC81804C 218*4882a593Smuzhiyun #define DMAC_SAR9 0xFC818050 219*4882a593Smuzhiyun #define DMAC_DAR9 0xFC818054 220*4882a593Smuzhiyun #define DMAC_TCR9 0xFC818058 221*4882a593Smuzhiyun #define DMAC_CHCR9 0xFC81805C 222*4882a593Smuzhiyun #define DMAC_DMAOR1 0xFC818060 223*4882a593Smuzhiyun #define DMAC_SAR10 0xFC818070 224*4882a593Smuzhiyun #define DMAC_DAR10 0xFC818074 225*4882a593Smuzhiyun #define DMAC_TCR10 0xFC818078 226*4882a593Smuzhiyun #define DMAC_CHCR10 0xFC81807C 227*4882a593Smuzhiyun #define DMAC_SAR11 0xFC818080 228*4882a593Smuzhiyun #define DMAC_DAR11 0xFC818084 229*4882a593Smuzhiyun #define DMAC_TCR11 0xFC818088 230*4882a593Smuzhiyun #define DMAC_CHCR11 0xFC81808C 231*4882a593Smuzhiyun #define DMAC_SARB6 0xFC818120 232*4882a593Smuzhiyun #define DMAC_DARB6 0xFC818124 233*4882a593Smuzhiyun #define DMAC_TCRB6 0xFC818128 234*4882a593Smuzhiyun #define DMAC_SARB7 0xFC818130 235*4882a593Smuzhiyun #define DMAC_DARB7 0xFC818134 236*4882a593Smuzhiyun #define DMAC_TCRB7 0xFC818138 237*4882a593Smuzhiyun #define DMAC_SARB8 0xFC818140 238*4882a593Smuzhiyun #define DMAC_DARB8 0xFC818144 239*4882a593Smuzhiyun #define DMAC_TCRB8 0xFC818148 240*4882a593Smuzhiyun #define DMAC_SARB9 0xFC818150 241*4882a593Smuzhiyun #define DMAC_DARB9 0xFC818154 242*4882a593Smuzhiyun #define DMAC_TCRB9 0xFC818158 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun /* Clock Pulse Generator */ 245*4882a593Smuzhiyun #define FRQCR 0xFFC80000 246*4882a593Smuzhiyun #define PLLCR 0xFFC80024 247*4882a593Smuzhiyun #define MSTPCR 0xFFC80030 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun /* Watchdog Timer and Reset */ 250*4882a593Smuzhiyun #define WTCNT WDTCNT 251*4882a593Smuzhiyun #define WDTST 0xFFCC0000 252*4882a593Smuzhiyun #define WDTCSR 0xFFCC0004 253*4882a593Smuzhiyun #define WDTBST 0xFFCC0008 254*4882a593Smuzhiyun #define WDTCNT 0xFFCC0010 255*4882a593Smuzhiyun #define WDTBCNT 0xFFCC0018 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun /* System Control */ 258*4882a593Smuzhiyun #define MSTPCR 0xFFC80030 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun /* Timer Unit */ 261*4882a593Smuzhiyun #define TMU_BASE 0xFFD80000 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun /* Timer/Counter */ 264*4882a593Smuzhiyun #define CMTCFG 0xFFE30000 265*4882a593Smuzhiyun #define CMTFRT 0xFFE30004 266*4882a593Smuzhiyun #define CMTCTL 0xFFE30008 267*4882a593Smuzhiyun #define CMTIRQS 0xFFE3000C 268*4882a593Smuzhiyun #define CMTCH0T 0xFFE30010 269*4882a593Smuzhiyun #define CMTCH0ST 0xFFE30020 270*4882a593Smuzhiyun #define CMTCH0C 0xFFE30030 271*4882a593Smuzhiyun #define CMTCH1T 0xFFE30014 272*4882a593Smuzhiyun #define CMTCH1ST 0xFFE30024 273*4882a593Smuzhiyun #define CMTCH1C 0xFFE30034 274*4882a593Smuzhiyun #define CMTCH2T 0xFFE30018 275*4882a593Smuzhiyun #define CMTCH2C 0xFFE30038 276*4882a593Smuzhiyun #define CMTCH3T 0xFFE3001C 277*4882a593Smuzhiyun #define CMTCH3C 0xFFE3003C 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun /* Realtime Clock */ 280*4882a593Smuzhiyun #define R64CNT 0xFFE80000 281*4882a593Smuzhiyun #define RSECCNT 0xFFE80004 282*4882a593Smuzhiyun #define RMINCNT 0xFFE80008 283*4882a593Smuzhiyun #define RHRCNT 0xFFE8000C 284*4882a593Smuzhiyun #define RWKCNT 0xFFE80010 285*4882a593Smuzhiyun #define RDAYCNT 0xFFE80014 286*4882a593Smuzhiyun #define RMONCNT 0xFFE80018 287*4882a593Smuzhiyun #define RYRCNT 0xFFE8001C 288*4882a593Smuzhiyun #define RSECAR 0xFFE80020 289*4882a593Smuzhiyun #define RMINAR 0xFFE80024 290*4882a593Smuzhiyun #define RHRAR 0xFFE80028 291*4882a593Smuzhiyun #define RWKAR 0xFFE8002C 292*4882a593Smuzhiyun #define RDAYAR 0xFFE80030 293*4882a593Smuzhiyun #define RMONAR 0xFFE80034 294*4882a593Smuzhiyun #define RCR1 0xFFE80038 295*4882a593Smuzhiyun #define RCR2 0xFFE8003C 296*4882a593Smuzhiyun #define RCR3 0xFFE80050 297*4882a593Smuzhiyun #define RYRAR 0xFFE80054 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun /* Serial Communication Interface with FIFO */ 300*4882a593Smuzhiyun #define SCSMR0 0xFFE00000 301*4882a593Smuzhiyun #define SCIF0_BASE SCSMR0 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun /* Serial I/O with FIFO */ 304*4882a593Smuzhiyun #define SIMDR 0xFFE20000 305*4882a593Smuzhiyun #define SISCR 0xFFE20002 306*4882a593Smuzhiyun #define SITDAR 0xFFE20004 307*4882a593Smuzhiyun #define SIRDAR 0xFFE20006 308*4882a593Smuzhiyun #define SICDAR 0xFFE20008 309*4882a593Smuzhiyun #define SICTR 0xFFE2000C 310*4882a593Smuzhiyun #define SIFCTR 0xFFE20010 311*4882a593Smuzhiyun #define SISTR 0xFFE20014 312*4882a593Smuzhiyun #define SIIER 0xFFE20016 313*4882a593Smuzhiyun #define SITCR 0xFFE20028 314*4882a593Smuzhiyun #define SIRCR 0xFFE2002C 315*4882a593Smuzhiyun #define SPICR 0xFFE20030 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun /* Serial Protocol Interface */ 318*4882a593Smuzhiyun #define SPCR 0xFFE50000 319*4882a593Smuzhiyun #define SPSR 0xFFE50004 320*4882a593Smuzhiyun #define SPSCR 0xFFE50008 321*4882a593Smuzhiyun #define SPTBR 0xFFE5000C 322*4882a593Smuzhiyun #define SPRBR 0xFFE50010 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun /* Multimedia Card Interface */ 325*4882a593Smuzhiyun #define CMDR0 0xFFE60000 326*4882a593Smuzhiyun #define CMDR1 0xFFE60001 327*4882a593Smuzhiyun #define CMDR2 0xFFE60002 328*4882a593Smuzhiyun #define CMDR3 0xFFE60003 329*4882a593Smuzhiyun #define CMDR4 0xFFE60004 330*4882a593Smuzhiyun #define CMDR5 0xFFE60005 331*4882a593Smuzhiyun #define CMDSTRT 0xFFE60006 332*4882a593Smuzhiyun #define OPCR 0xFFE6000A 333*4882a593Smuzhiyun #define CSTR 0xFFE6000B 334*4882a593Smuzhiyun #define INTCR0 0xFFE6000C 335*4882a593Smuzhiyun #define INTCR1 0xFFE6000D 336*4882a593Smuzhiyun #define INTSTR0 0xFFE6000E 337*4882a593Smuzhiyun #define INTSTR1 0xFFE6000F 338*4882a593Smuzhiyun #define CLKON 0xFFE60010 339*4882a593Smuzhiyun #define CTOCR 0xFFE60011 340*4882a593Smuzhiyun #define TBCR 0xFFE60014 341*4882a593Smuzhiyun #define MODER 0xFFE60016 342*4882a593Smuzhiyun #define CMDTYR 0xFFE60018 343*4882a593Smuzhiyun #define RSPTYR 0xFFE60019 344*4882a593Smuzhiyun #define TBNCR 0xFFE6001A 345*4882a593Smuzhiyun #define RSPR0 0xFFE60020 346*4882a593Smuzhiyun #define RSPR1 0xFFE60021 347*4882a593Smuzhiyun #define RSPR2 0xFFE60022 348*4882a593Smuzhiyun #define RSPR3 0xFFE60023 349*4882a593Smuzhiyun #define RSPR4 0xFFE60024 350*4882a593Smuzhiyun #define RSPR5 0xFFE60025 351*4882a593Smuzhiyun #define RSPR6 0xFFE60026 352*4882a593Smuzhiyun #define RSPR7 0xFFE60027 353*4882a593Smuzhiyun #define RSPR8 0xFFE60028 354*4882a593Smuzhiyun #define RSPR9 0xFFE60029 355*4882a593Smuzhiyun #define RSPR10 0xFFE6002A 356*4882a593Smuzhiyun #define RSPR11 0xFFE6002B 357*4882a593Smuzhiyun #define RSPR12 0xFFE6002C 358*4882a593Smuzhiyun #define RSPR13 0xFFE6002D 359*4882a593Smuzhiyun #define RSPR14 0xFFE6002E 360*4882a593Smuzhiyun #define RSPR15 0xFFE6002F 361*4882a593Smuzhiyun #define RSPR16 0xFFE60030 362*4882a593Smuzhiyun #define RSPRD 0xFFE60031 363*4882a593Smuzhiyun #define DTOUTR 0xFFE60032 364*4882a593Smuzhiyun #define DR 0xFFE60040 365*4882a593Smuzhiyun #define DMACR 0xFFE60044 366*4882a593Smuzhiyun #define INTCR2 0xFFE60046 367*4882a593Smuzhiyun #define INTSTR2 0xFFE60048 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun /* Audio Codec Interface */ 370*4882a593Smuzhiyun #define HACCR 0xFFE40008 371*4882a593Smuzhiyun #define HACCSAR 0xFFE40020 372*4882a593Smuzhiyun #define HACCSDR 0xFFE40024 373*4882a593Smuzhiyun #define HACPCML 0xFFE40028 374*4882a593Smuzhiyun #define HACPCMR 0xFFE4002C 375*4882a593Smuzhiyun #define HACTIER 0xFFE40050 376*4882a593Smuzhiyun #define HACTSR 0xFFE40054 377*4882a593Smuzhiyun #define HACRIER 0xFFE40058 378*4882a593Smuzhiyun #define HACRSR 0xFFE4005C 379*4882a593Smuzhiyun #define HACACR 0xFFE40060 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun /* Serial Sound Interface */ 382*4882a593Smuzhiyun #define SSICR 0xFFE70000 383*4882a593Smuzhiyun #define SSISR 0xFFE70004 384*4882a593Smuzhiyun #define SSITDR 0xFFE70008 385*4882a593Smuzhiyun #define SSIRDR 0xFFE7000C 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun /* Flash memory Controller */ 388*4882a593Smuzhiyun #define FLCMNCR 0xFFE90000 389*4882a593Smuzhiyun #define FLCMDCR 0xFFE90004 390*4882a593Smuzhiyun #define FLCMCDR 0xFFE90008 391*4882a593Smuzhiyun #define FLADR 0xFFE9000C 392*4882a593Smuzhiyun #define FLDATAR 0xFFE90010 393*4882a593Smuzhiyun #define FLDTCNTR 0xFFE90014 394*4882a593Smuzhiyun #define FLINTDMACR 0xFFE90018 395*4882a593Smuzhiyun #define FLBSYTMR 0xFFE9001C 396*4882a593Smuzhiyun #define FLBSYCNT 0xFFE90020 397*4882a593Smuzhiyun #define FLTRCR 0xFFE9002C 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun /* General Purpose I/O */ 400*4882a593Smuzhiyun #define PACR 0xFFEA0000 401*4882a593Smuzhiyun #define PBCR 0xFFEA0002 402*4882a593Smuzhiyun #define PCCR 0xFFEA0004 403*4882a593Smuzhiyun #define PDCR 0xFFEA0006 404*4882a593Smuzhiyun #define PECR 0xFFEA0008 405*4882a593Smuzhiyun #define PFCR 0xFFEA000A 406*4882a593Smuzhiyun #define PGCR 0xFFEA000C 407*4882a593Smuzhiyun #define PHCR 0xFFEA000E 408*4882a593Smuzhiyun #define PJCR 0xFFEA0010 409*4882a593Smuzhiyun #define PKCR 0xFFEA0012 410*4882a593Smuzhiyun #define PLCR 0xFFEA0014 411*4882a593Smuzhiyun #define PMCR 0xFFEA0016 412*4882a593Smuzhiyun #define PADR 0xFFEA0020 413*4882a593Smuzhiyun #define PBDR 0xFFEA0022 414*4882a593Smuzhiyun #define PCDR 0xFFEA0024 415*4882a593Smuzhiyun #define PDDR 0xFFEA0026 416*4882a593Smuzhiyun #define PEDR 0xFFEA0028 417*4882a593Smuzhiyun #define PFDR 0xFFEA002A 418*4882a593Smuzhiyun #define PGDR 0xFFEA002C 419*4882a593Smuzhiyun #define PHDR 0xFFEA002E 420*4882a593Smuzhiyun #define PJDR 0xFFEA0030 421*4882a593Smuzhiyun #define PKDR 0xFFEA0032 422*4882a593Smuzhiyun #define PLDR 0xFFEA0034 423*4882a593Smuzhiyun #define PMDR 0xFFEA0036 424*4882a593Smuzhiyun #define PEPUPR 0xFFEA0048 425*4882a593Smuzhiyun #define PHPUPR 0xFFEA004E 426*4882a593Smuzhiyun #define PJPUPR 0xFFEA0050 427*4882a593Smuzhiyun #define PKPUPR 0xFFEA0052 428*4882a593Smuzhiyun #define PMPUPR 0xFFEA0056 429*4882a593Smuzhiyun #define PPUPR1 0xFFEA0060 430*4882a593Smuzhiyun #define PPUPR2 0xFFEA0062 431*4882a593Smuzhiyun #define PMSELR 0xFFEA0080 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun /* User Break Controller */ 434*4882a593Smuzhiyun #define CBR0 0xFF200000 435*4882a593Smuzhiyun #define CRR0 0xFF200004 436*4882a593Smuzhiyun #define CAR0 0xFF200008 437*4882a593Smuzhiyun #define CAMR0 0xFF20000C 438*4882a593Smuzhiyun #define CBR1 0xFF200020 439*4882a593Smuzhiyun #define CRR1 0xFF200024 440*4882a593Smuzhiyun #define CAR1 0xFF200028 441*4882a593Smuzhiyun #define CAMR1 0xFF20002C 442*4882a593Smuzhiyun #define CDR1 0xFF200030 443*4882a593Smuzhiyun #define CDMR1 0xFF200034 444*4882a593Smuzhiyun #define CETR1 0xFF200038 445*4882a593Smuzhiyun #define CCMFR 0xFF200600 446*4882a593Smuzhiyun #define CBCR 0xFF200620 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun #endif /* _ASM_CPU_SH7780_H_ */ 449