1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2012 Renesas Solutions Corp. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ASM_CPU_SH7752_H_ 8*4882a593Smuzhiyun #define _ASM_CPU_SH7752_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define CCR 0xFF00001C 11*4882a593Smuzhiyun #define WTCNT 0xFFCC0000 12*4882a593Smuzhiyun #define CCR_CACHE_INIT 0x0000090b 13*4882a593Smuzhiyun #define CACHE_OC_NUM_WAYS 1 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef __ASSEMBLY__ /* put C only stuff in this section */ 16*4882a593Smuzhiyun /* MMU */ 17*4882a593Smuzhiyun struct mmu_regs { 18*4882a593Smuzhiyun unsigned int reserved[4]; 19*4882a593Smuzhiyun unsigned int mmucr; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun #define MMU_BASE ((struct mmu_regs *)0xff000000) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* Watchdog */ 24*4882a593Smuzhiyun #define WTCSR0 0xffcc0002 25*4882a593Smuzhiyun #define WRSTCSR_R 0xffcc0003 26*4882a593Smuzhiyun #define WRSTCSR_W 0xffcc0002 27*4882a593Smuzhiyun #define WTCSR_PREFIX 0xa500 28*4882a593Smuzhiyun #define WRSTCSR_PREFIX 0x6900 29*4882a593Smuzhiyun #define WRSTCSR_WOVF_PREFIX 0x9600 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* SCIF */ 32*4882a593Smuzhiyun #define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */ 33*4882a593Smuzhiyun #define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */ 34*4882a593Smuzhiyun #define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* TMU0 */ 37*4882a593Smuzhiyun #define TMU_BASE 0xFE430000 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* ETHER, GETHER MAC address */ 40*4882a593Smuzhiyun struct ether_mac_regs { 41*4882a593Smuzhiyun unsigned int reserved[114]; 42*4882a593Smuzhiyun unsigned int mahr; 43*4882a593Smuzhiyun unsigned int reserved2; 44*4882a593Smuzhiyun unsigned int malr; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun #define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400) 47*4882a593Smuzhiyun #define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00) 48*4882a593Smuzhiyun #define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000) 49*4882a593Smuzhiyun #define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* GETHER */ 52*4882a593Smuzhiyun struct gether_control_regs { 53*4882a593Smuzhiyun unsigned int gbecont; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun #define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100) 56*4882a593Smuzhiyun #define GBECONT_RMII1 0x00020000 57*4882a593Smuzhiyun #define GBECONT_RMII0 0x00010000 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* SerMux */ 60*4882a593Smuzhiyun struct sermux_regs { 61*4882a593Smuzhiyun unsigned char smr0; 62*4882a593Smuzhiyun unsigned char smr1; 63*4882a593Smuzhiyun unsigned char smr2; 64*4882a593Smuzhiyun unsigned char smr3; 65*4882a593Smuzhiyun unsigned char smr4; 66*4882a593Smuzhiyun unsigned char smr5; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun #define SERMUX_BASE ((struct sermux_regs *)0xfe470000) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* USB0/1 */ 72*4882a593Smuzhiyun struct usb_common_regs { 73*4882a593Smuzhiyun unsigned short reserved[129]; 74*4882a593Smuzhiyun unsigned short suspmode; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun #define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000) 77*4882a593Smuzhiyun #define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun struct usb0_phy_regs { 80*4882a593Smuzhiyun unsigned short reset; 81*4882a593Smuzhiyun unsigned short reserved[4]; 82*4882a593Smuzhiyun unsigned short portsel; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun #define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun struct usb1_port_regs { 87*4882a593Smuzhiyun unsigned int port1sel; 88*4882a593Smuzhiyun unsigned int reserved; 89*4882a593Smuzhiyun unsigned int usb1intsts; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun #define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct usb1_alignment_regs { 94*4882a593Smuzhiyun unsigned int ehcidatac; /* 0xfe4fe018 */ 95*4882a593Smuzhiyun unsigned int reserved[63]; 96*4882a593Smuzhiyun unsigned int ohcidatac; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun #define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018) 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* GPIO */ 101*4882a593Smuzhiyun struct gpio_regs { 102*4882a593Smuzhiyun unsigned short pacr; 103*4882a593Smuzhiyun unsigned short pbcr; 104*4882a593Smuzhiyun unsigned short pccr; 105*4882a593Smuzhiyun unsigned short pdcr; 106*4882a593Smuzhiyun unsigned short pecr; 107*4882a593Smuzhiyun unsigned short pfcr; 108*4882a593Smuzhiyun unsigned short pgcr; 109*4882a593Smuzhiyun unsigned short phcr; 110*4882a593Smuzhiyun unsigned short picr; 111*4882a593Smuzhiyun unsigned short pjcr; 112*4882a593Smuzhiyun unsigned short pkcr; 113*4882a593Smuzhiyun unsigned short plcr; 114*4882a593Smuzhiyun unsigned short pmcr; 115*4882a593Smuzhiyun unsigned short pncr; 116*4882a593Smuzhiyun unsigned short pocr; 117*4882a593Smuzhiyun unsigned short reserved; 118*4882a593Smuzhiyun unsigned short pqcr; 119*4882a593Smuzhiyun unsigned short prcr; 120*4882a593Smuzhiyun unsigned short pscr; 121*4882a593Smuzhiyun unsigned short ptcr; 122*4882a593Smuzhiyun unsigned short pucr; 123*4882a593Smuzhiyun unsigned short pvcr; 124*4882a593Smuzhiyun unsigned short pwcr; 125*4882a593Smuzhiyun unsigned short pxcr; 126*4882a593Smuzhiyun unsigned short pycr; 127*4882a593Smuzhiyun unsigned short pzcr; 128*4882a593Smuzhiyun unsigned char padr; 129*4882a593Smuzhiyun unsigned char reserved_a; 130*4882a593Smuzhiyun unsigned char pbdr; 131*4882a593Smuzhiyun unsigned char reserved_b; 132*4882a593Smuzhiyun unsigned char pcdr; 133*4882a593Smuzhiyun unsigned char reserved_c; 134*4882a593Smuzhiyun unsigned char pddr; 135*4882a593Smuzhiyun unsigned char reserved_d; 136*4882a593Smuzhiyun unsigned char pedr; 137*4882a593Smuzhiyun unsigned char reserved_e; 138*4882a593Smuzhiyun unsigned char pfdr; 139*4882a593Smuzhiyun unsigned char reserved_f; 140*4882a593Smuzhiyun unsigned char pgdr; 141*4882a593Smuzhiyun unsigned char reserved_g; 142*4882a593Smuzhiyun unsigned char phdr; 143*4882a593Smuzhiyun unsigned char reserved_h; 144*4882a593Smuzhiyun unsigned char pidr; 145*4882a593Smuzhiyun unsigned char reserved_i; 146*4882a593Smuzhiyun unsigned char pjdr; 147*4882a593Smuzhiyun unsigned char reserved_j; 148*4882a593Smuzhiyun unsigned char pkdr; 149*4882a593Smuzhiyun unsigned char reserved_k; 150*4882a593Smuzhiyun unsigned char pldr; 151*4882a593Smuzhiyun unsigned char reserved_l; 152*4882a593Smuzhiyun unsigned char pmdr; 153*4882a593Smuzhiyun unsigned char reserved_m; 154*4882a593Smuzhiyun unsigned char pndr; 155*4882a593Smuzhiyun unsigned char reserved_n; 156*4882a593Smuzhiyun unsigned char podr; 157*4882a593Smuzhiyun unsigned char reserved_o; 158*4882a593Smuzhiyun unsigned char ppdr; 159*4882a593Smuzhiyun unsigned char reserved_p; 160*4882a593Smuzhiyun unsigned char pqdr; 161*4882a593Smuzhiyun unsigned char reserved_q; 162*4882a593Smuzhiyun unsigned char prdr; 163*4882a593Smuzhiyun unsigned char reserved_r; 164*4882a593Smuzhiyun unsigned char psdr; 165*4882a593Smuzhiyun unsigned char reserved_s; 166*4882a593Smuzhiyun unsigned char ptdr; 167*4882a593Smuzhiyun unsigned char reserved_t; 168*4882a593Smuzhiyun unsigned char pudr; 169*4882a593Smuzhiyun unsigned char reserved_u; 170*4882a593Smuzhiyun unsigned char pvdr; 171*4882a593Smuzhiyun unsigned char reserved_v; 172*4882a593Smuzhiyun unsigned char pwdr; 173*4882a593Smuzhiyun unsigned char reserved_w; 174*4882a593Smuzhiyun unsigned char pxdr; 175*4882a593Smuzhiyun unsigned char reserved_x; 176*4882a593Smuzhiyun unsigned char pydr; 177*4882a593Smuzhiyun unsigned char reserved_y; 178*4882a593Smuzhiyun unsigned char pzdr; 179*4882a593Smuzhiyun unsigned char reserved_z; 180*4882a593Smuzhiyun unsigned short ncer; 181*4882a593Smuzhiyun unsigned short ncmcr; 182*4882a593Smuzhiyun unsigned short nccsr; 183*4882a593Smuzhiyun unsigned char reserved2[2]; 184*4882a593Smuzhiyun unsigned short psel0; /* +0x70 */ 185*4882a593Smuzhiyun unsigned short psel1; 186*4882a593Smuzhiyun unsigned short psel2; 187*4882a593Smuzhiyun unsigned short psel3; 188*4882a593Smuzhiyun unsigned short psel4; 189*4882a593Smuzhiyun unsigned short psel5; 190*4882a593Smuzhiyun unsigned short psel6; 191*4882a593Smuzhiyun unsigned short reserved3[2]; 192*4882a593Smuzhiyun unsigned short psel7; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun #define GPIO_BASE ((struct gpio_regs *)0xffec0000) 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun #endif /* ifndef __ASSEMBLY__ */ 197*4882a593Smuzhiyun #endif /* _ASM_CPU_SH7752_H_ */ 198