1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2007 (C) 3*4882a593Smuzhiyun * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2008 (C) 6*4882a593Smuzhiyun * Mark Jonas <mark.jonas@de.bosch.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SH7720 Internal I/O register 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef _ASM_CPU_SH7720_H_ 14*4882a593Smuzhiyun #define _ASM_CPU_SH7720_H_ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CACHE_OC_NUM_WAYS 4 17*4882a593Smuzhiyun #define CCR_CACHE_INIT 0x0000000B 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* EXP */ 20*4882a593Smuzhiyun #define TRA 0xFFFFFFD0 21*4882a593Smuzhiyun #define EXPEVT 0xFFFFFFD4 22*4882a593Smuzhiyun #define INTEVT 0xFFFFFFD8 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* MMU */ 25*4882a593Smuzhiyun #define MMUCR 0xFFFFFFE0 26*4882a593Smuzhiyun #define PTEH 0xFFFFFFF0 27*4882a593Smuzhiyun #define PTEL 0xFFFFFFF4 28*4882a593Smuzhiyun #define TTB 0xFFFFFFF8 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* CACHE */ 31*4882a593Smuzhiyun #define CCR 0xFFFFFFEC 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* INTC */ 34*4882a593Smuzhiyun #define IPRF 0xA4080000 35*4882a593Smuzhiyun #define IPRG 0xA4080002 36*4882a593Smuzhiyun #define IPRH 0xA4080004 37*4882a593Smuzhiyun #define IPRI 0xA4080006 38*4882a593Smuzhiyun #define IPRJ 0xA4080008 39*4882a593Smuzhiyun #define IRR5 0xA4080020 40*4882a593Smuzhiyun #define IRR6 0xA4080022 41*4882a593Smuzhiyun #define IRR7 0xA4080024 42*4882a593Smuzhiyun #define IRR8 0xA4080026 43*4882a593Smuzhiyun #define IRR9 0xA4080028 44*4882a593Smuzhiyun #define IRR0 0xA4140004 45*4882a593Smuzhiyun #define IRR1 0xA4140006 46*4882a593Smuzhiyun #define IRR2 0xA4140008 47*4882a593Smuzhiyun #define IRR3 0xA414000A 48*4882a593Smuzhiyun #define IRR4 0xA414000C 49*4882a593Smuzhiyun #define ICR1 0xA4140010 50*4882a593Smuzhiyun #define ICR2 0xA4140012 51*4882a593Smuzhiyun #define PINTER 0xA4140014 52*4882a593Smuzhiyun #define IPRC 0xA4140016 53*4882a593Smuzhiyun #define IPRD 0xA4140018 54*4882a593Smuzhiyun #define IPRE 0xA414001A 55*4882a593Smuzhiyun #define ICR0 0xA414FEE0 56*4882a593Smuzhiyun #define IPRA 0xA414FEE2 57*4882a593Smuzhiyun #define IPRB 0xA414FEE4 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* BSC */ 60*4882a593Smuzhiyun #define BSC_BASE 0xA4FD0000 61*4882a593Smuzhiyun #define CMNCR (BSC_BASE + 0x00) 62*4882a593Smuzhiyun #define CS0BCR (BSC_BASE + 0x04) 63*4882a593Smuzhiyun #define CS2BCR (BSC_BASE + 0x08) 64*4882a593Smuzhiyun #define CS3BCR (BSC_BASE + 0x0C) 65*4882a593Smuzhiyun #define CS4BCR (BSC_BASE + 0x10) 66*4882a593Smuzhiyun #define CS5ABCR (BSC_BASE + 0x14) 67*4882a593Smuzhiyun #define CS5BBCR (BSC_BASE + 0x18) 68*4882a593Smuzhiyun #define CS6ABCR (BSC_BASE + 0x1C) 69*4882a593Smuzhiyun #define CS6BBCR (BSC_BASE + 0x20) 70*4882a593Smuzhiyun #define CS0WCR (BSC_BASE + 0x24) 71*4882a593Smuzhiyun #define CS2WCR (BSC_BASE + 0x28) 72*4882a593Smuzhiyun #define CS3WCR (BSC_BASE + 0x2C) 73*4882a593Smuzhiyun #define CS4WCR (BSC_BASE + 0x30) 74*4882a593Smuzhiyun #define CS5AWCR (BSC_BASE + 0x34) 75*4882a593Smuzhiyun #define CS5BWCR (BSC_BASE + 0x38) 76*4882a593Smuzhiyun #define CS6AWCR (BSC_BASE + 0x3C) 77*4882a593Smuzhiyun #define CS6BWCR (BSC_BASE + 0x40) 78*4882a593Smuzhiyun #define SDCR (BSC_BASE + 0x44) 79*4882a593Smuzhiyun #define RTCSR (BSC_BASE + 0x48) 80*4882a593Smuzhiyun #define RTCNR (BSC_BASE + 0x4C) 81*4882a593Smuzhiyun #define RTCOR (BSC_BASE + 0x50) 82*4882a593Smuzhiyun #define SDMR2 (BSC_BASE + 0x4000) 83*4882a593Smuzhiyun #define SDMR3 (BSC_BASE + 0x5000) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* DMAC */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* CPG */ 88*4882a593Smuzhiyun #define UCLKCR 0xA40A0008 89*4882a593Smuzhiyun #define FRQCR 0xA415FF80 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* LOW POWER MODE */ 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* TMU */ 94*4882a593Smuzhiyun #define TMU_BASE 0xA412FE90 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* TPU */ 97*4882a593Smuzhiyun #define TPU_BASE 0xA4480000 98*4882a593Smuzhiyun #define TPU_TSTR (TPU_BASE + 0x00) 99*4882a593Smuzhiyun #define TPU_TCR0 (TPU_BASE + 0x10) 100*4882a593Smuzhiyun #define TPU_TMDR0 (TPU_BASE + 0x14) 101*4882a593Smuzhiyun #define TPU_TIOR0 (TPU_BASE + 0x18) 102*4882a593Smuzhiyun #define TPU_TIER0 (TPU_BASE + 0x1C) 103*4882a593Smuzhiyun #define TPU_TSR0 (TPU_BASE + 0x20) 104*4882a593Smuzhiyun #define TPU_TCNT0 (TPU_BASE + 0x24) 105*4882a593Smuzhiyun #define TPU_TGRA0 (TPU_BASE + 0x28) 106*4882a593Smuzhiyun #define TPU_TGRB0 (TPU_BASE + 0x2C) 107*4882a593Smuzhiyun #define TPU_TGRC0 (TPU_BASE + 0x30) 108*4882a593Smuzhiyun #define TPU_TGRD0 (TPU_BASE + 0x34) 109*4882a593Smuzhiyun #define TPU_TCR1 (TPU_BASE + 0x50) 110*4882a593Smuzhiyun #define TPU_TMDR1 (TPU_BASE + 0x54) 111*4882a593Smuzhiyun #define TPU_TIOR1 (TPU_BASE + 0x58) 112*4882a593Smuzhiyun #define TPU_TIER1 (TPU_BASE + 0x5C) 113*4882a593Smuzhiyun #define TPU_TSR1 (TPU_BASE + 0x60) 114*4882a593Smuzhiyun #define TPU_TCNT1 (TPU_BASE + 0x64) 115*4882a593Smuzhiyun #define TPU_TGRA1 (TPU_BASE + 0x68) 116*4882a593Smuzhiyun #define TPU_TGRB1 (TPU_BASE + 0x6C) 117*4882a593Smuzhiyun #define TPU_TGRC1 (TPU_BASE + 0x70) 118*4882a593Smuzhiyun #define TPU_TGRD1 (TPU_BASE + 0x74) 119*4882a593Smuzhiyun #define TPU_TCR2 (TPU_BASE + 0x90) 120*4882a593Smuzhiyun #define TPU_TMDR2 (TPU_BASE + 0x94) 121*4882a593Smuzhiyun #define TPU_TIOR2 (TPU_BASE + 0x98) 122*4882a593Smuzhiyun #define TPU_TIER2 (TPU_BASE + 0x9C) 123*4882a593Smuzhiyun #define TPU_TSR2 (TPU_BASE + 0xB0) 124*4882a593Smuzhiyun #define TPU_TCNT2 (TPU_BASE + 0xB4) 125*4882a593Smuzhiyun #define TPU_TGRA2 (TPU_BASE + 0xB8) 126*4882a593Smuzhiyun #define TPU_TGRB2 (TPU_BASE + 0xBC) 127*4882a593Smuzhiyun #define TPU_TGRC2 (TPU_BASE + 0xC0) 128*4882a593Smuzhiyun #define TPU_TGRD2 (TPU_BASE + 0xC4) 129*4882a593Smuzhiyun #define TPU_TCR3 (TPU_BASE + 0xD0) 130*4882a593Smuzhiyun #define TPU_TMDR3 (TPU_BASE + 0xD4) 131*4882a593Smuzhiyun #define TPU_TIOR3 (TPU_BASE + 0xD8) 132*4882a593Smuzhiyun #define TPU_TIER3 (TPU_BASE + 0xDC) 133*4882a593Smuzhiyun #define TPU_TSR3 (TPU_BASE + 0xE0) 134*4882a593Smuzhiyun #define TPU_TCNT3 (TPU_BASE + 0xE4) 135*4882a593Smuzhiyun #define TPU_TGRA3 (TPU_BASE + 0xE8) 136*4882a593Smuzhiyun #define TPU_TGRB3 (TPU_BASE + 0xEC) 137*4882a593Smuzhiyun #define TPU_TGRC3 (TPU_BASE + 0xF0) 138*4882a593Smuzhiyun #define TPU_TGRD3 (TPU_BASE + 0xF4) 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /* CMT */ 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* SIOF */ 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* SCIF */ 145*4882a593Smuzhiyun #define SCIF0_BASE 0xA4430000 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun /* SIM */ 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun /* IrDA */ 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* IIC */ 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* LCDC */ 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun /* USBF */ 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun /* MMCIF */ 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun /* PFC */ 160*4882a593Smuzhiyun #define PFC_BASE 0xA4050100 161*4882a593Smuzhiyun #define PACR (PFC_BASE + 0x00) 162*4882a593Smuzhiyun #define PBCR (PFC_BASE + 0x02) 163*4882a593Smuzhiyun #define PCCR (PFC_BASE + 0x04) 164*4882a593Smuzhiyun #define PDCR (PFC_BASE + 0x06) 165*4882a593Smuzhiyun #define PECR (PFC_BASE + 0x08) 166*4882a593Smuzhiyun #define PFCR (PFC_BASE + 0x0A) 167*4882a593Smuzhiyun #define PGCR (PFC_BASE + 0x0C) 168*4882a593Smuzhiyun #define PHCR (PFC_BASE + 0x0E) 169*4882a593Smuzhiyun #define PJCR (PFC_BASE + 0x10) 170*4882a593Smuzhiyun #define PKCR (PFC_BASE + 0x12) 171*4882a593Smuzhiyun #define PLCR (PFC_BASE + 0x14) 172*4882a593Smuzhiyun #define PMCR (PFC_BASE + 0x16) 173*4882a593Smuzhiyun #define PPCR (PFC_BASE + 0x18) 174*4882a593Smuzhiyun #define PRCR (PFC_BASE + 0x1A) 175*4882a593Smuzhiyun #define PSCR (PFC_BASE + 0x1C) 176*4882a593Smuzhiyun #define PTCR (PFC_BASE + 0x1E) 177*4882a593Smuzhiyun #define PUCR (PFC_BASE + 0x20) 178*4882a593Smuzhiyun #define PVCR (PFC_BASE + 0x22) 179*4882a593Smuzhiyun #define PSELA (PFC_BASE + 0x24) 180*4882a593Smuzhiyun #define PSELB (PFC_BASE + 0x26) 181*4882a593Smuzhiyun #define PSELC (PFC_BASE + 0x28) 182*4882a593Smuzhiyun #define PSELD (PFC_BASE + 0x2A) 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun /* I/O Port */ 185*4882a593Smuzhiyun #define PORT_BASE 0xA4050100 186*4882a593Smuzhiyun #define PADR (PORT_BASE + 0x40) 187*4882a593Smuzhiyun #define PBDR (PORT_BASE + 0x42) 188*4882a593Smuzhiyun #define PCDR (PORT_BASE + 0x44) 189*4882a593Smuzhiyun #define PDDR (PORT_BASE + 0x46) 190*4882a593Smuzhiyun #define PEDR (PORT_BASE + 0x48) 191*4882a593Smuzhiyun #define PFDR (PORT_BASE + 0x4A) 192*4882a593Smuzhiyun #define PGDR (PORT_BASE + 0x4C) 193*4882a593Smuzhiyun #define PHDR (PORT_BASE + 0x4E) 194*4882a593Smuzhiyun #define PJDR (PORT_BASE + 0x50) 195*4882a593Smuzhiyun #define PKDR (PORT_BASE + 0x52) 196*4882a593Smuzhiyun #define PLDR (PORT_BASE + 0x54) 197*4882a593Smuzhiyun #define PMDR (PORT_BASE + 0x56) 198*4882a593Smuzhiyun #define PPDR (PORT_BASE + 0x58) 199*4882a593Smuzhiyun #define PRDR (PORT_BASE + 0x5A) 200*4882a593Smuzhiyun #define PSDR (PORT_BASE + 0x5C) 201*4882a593Smuzhiyun #define PTDR (PORT_BASE + 0x5E) 202*4882a593Smuzhiyun #define PUDR (PORT_BASE + 0x60) 203*4882a593Smuzhiyun #define PVDR (PORT_BASE + 0x62) 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun /* H-UDI */ 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun #endif /* _ASM_CPU_SH7720_H_ */ 208