1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ASM_CPU_SH4_H_ 8*4882a593Smuzhiyun #define _ASM_CPU_SH4_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* cache control */ 11*4882a593Smuzhiyun #define CCR_CACHE_STOP 0x00000808 12*4882a593Smuzhiyun #define CCR_CACHE_ENABLE 0x00000101 13*4882a593Smuzhiyun #define CCR_CACHE_ICI 0x00000800 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CACHE_OC_ADDRESS_ARRAY 0xf4000000 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #if defined (CONFIG_CPU_SH7750) || \ 18*4882a593Smuzhiyun defined(CONFIG_CPU_SH7751) 19*4882a593Smuzhiyun #define CACHE_OC_WAY_SHIFT 14 20*4882a593Smuzhiyun #define CACHE_OC_NUM_ENTRIES 512 21*4882a593Smuzhiyun #else 22*4882a593Smuzhiyun #define CACHE_OC_WAY_SHIFT 13 23*4882a593Smuzhiyun #define CACHE_OC_NUM_ENTRIES 256 24*4882a593Smuzhiyun #endif 25*4882a593Smuzhiyun #define CACHE_OC_ENTRY_SHIFT 5 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #if defined (CONFIG_CPU_SH7750) || \ 28*4882a593Smuzhiyun defined(CONFIG_CPU_SH7751) 29*4882a593Smuzhiyun # include <asm/cpu_sh7750.h> 30*4882a593Smuzhiyun #elif defined (CONFIG_CPU_SH7722) 31*4882a593Smuzhiyun # include <asm/cpu_sh7722.h> 32*4882a593Smuzhiyun #elif defined (CONFIG_CPU_SH7723) 33*4882a593Smuzhiyun # include <asm/cpu_sh7723.h> 34*4882a593Smuzhiyun #elif defined (CONFIG_CPU_SH7724) 35*4882a593Smuzhiyun # include <asm/cpu_sh7724.h> 36*4882a593Smuzhiyun #elif defined (CONFIG_CPU_SH7734) 37*4882a593Smuzhiyun # include <asm/cpu_sh7734.h> 38*4882a593Smuzhiyun #elif defined (CONFIG_CPU_SH7752) 39*4882a593Smuzhiyun # include <asm/cpu_sh7752.h> 40*4882a593Smuzhiyun #elif defined (CONFIG_CPU_SH7753) 41*4882a593Smuzhiyun # include <asm/cpu_sh7753.h> 42*4882a593Smuzhiyun #elif defined (CONFIG_CPU_SH7757) 43*4882a593Smuzhiyun # include <asm/cpu_sh7757.h> 44*4882a593Smuzhiyun #elif defined (CONFIG_CPU_SH7763) 45*4882a593Smuzhiyun # include <asm/cpu_sh7763.h> 46*4882a593Smuzhiyun #elif defined (CONFIG_CPU_SH7780) 47*4882a593Smuzhiyun # include <asm/cpu_sh7780.h> 48*4882a593Smuzhiyun #elif defined (CONFIG_CPU_SH7785) 49*4882a593Smuzhiyun # include <asm/cpu_sh7785.h> 50*4882a593Smuzhiyun #else 51*4882a593Smuzhiyun # error "Unknown SH4 variant" 52*4882a593Smuzhiyun #endif 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #if defined(CONFIG_SH_32BIT) 55*4882a593Smuzhiyun #define PMB_ADDR_ARRAY 0xf6100000 56*4882a593Smuzhiyun #define PMB_ADDR_ENTRY 8 57*4882a593Smuzhiyun #define PMB_VPN 24 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define PMB_DATA_ARRAY 0xf7100000 60*4882a593Smuzhiyun #define PMB_DATA_ENTRY 8 61*4882a593Smuzhiyun #define PMB_PPN 24 62*4882a593Smuzhiyun #define PMB_UB 9 /* Buffered write */ 63*4882a593Smuzhiyun #define PMB_V 8 /* Valid */ 64*4882a593Smuzhiyun #define PMB_SZ1 7 /* Page size (upper bit) */ 65*4882a593Smuzhiyun #define PMB_SZ0 4 /* Page size (lower bit) */ 66*4882a593Smuzhiyun #define PMB_C 3 /* Cacheability */ 67*4882a593Smuzhiyun #define PMB_WT 0 /* Write-through */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY)) 70*4882a593Smuzhiyun #define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY)) 71*4882a593Smuzhiyun #define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN)) 72*4882a593Smuzhiyun #define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \ 73*4882a593Smuzhiyun ((ppn << PMB_PPN) | (ub << PMB_UB) | \ 74*4882a593Smuzhiyun (v << PMB_V) | (sz1 << PMB_SZ1) | \ 75*4882a593Smuzhiyun (sz0 << PMB_SZ0) | (c << PMB_C) | \ 76*4882a593Smuzhiyun (wt << PMB_WT)) 77*4882a593Smuzhiyun #endif 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #endif /* _ASM_CPU_SH4_H_ */ 80