xref: /OK3568_Linux_fs/u-boot/arch/sh/cpu/sh4/watchdog.c (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
3*4882a593Smuzhiyun  */
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun #include <common.h>
6*4882a593Smuzhiyun #include <asm/processor.h>
7*4882a593Smuzhiyun #include <asm/system.h>
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #define WDT_BASE	WTCNT
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #define WDT_WD		(1 << 6)
13*4882a593Smuzhiyun #define WDT_RST_P	(0)
14*4882a593Smuzhiyun #define WDT_RST_M	(1 << 5)
15*4882a593Smuzhiyun #define WDT_ENABLE	(1 << 7)
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #if defined(CONFIG_WATCHDOG)
csr_read(void)18*4882a593Smuzhiyun static unsigned char csr_read(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun 	return inb(WDT_BASE + 0x04);
21*4882a593Smuzhiyun }
22*4882a593Smuzhiyun 
cnt_write(unsigned char value)23*4882a593Smuzhiyun static void cnt_write(unsigned char value)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun 	outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00);
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun 
csr_write(unsigned char value)28*4882a593Smuzhiyun static void csr_write(unsigned char value)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun 	outl((unsigned short)value | 0xA500, WDT_BASE + 0x04);
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun 
watchdog_reset(void)33*4882a593Smuzhiyun void watchdog_reset(void)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun 	outl(0x55000000, WDT_BASE + 0x08);
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun 
watchdog_init(void)38*4882a593Smuzhiyun int watchdog_init(void)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun 	/* Set overflow time*/
41*4882a593Smuzhiyun 	cnt_write(0);
42*4882a593Smuzhiyun 	/* Power on reset */
43*4882a593Smuzhiyun 	csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	return 0;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun 
watchdog_disable(void)48*4882a593Smuzhiyun int watchdog_disable(void)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun 	csr_write(csr_read() & ~WDT_ENABLE);
51*4882a593Smuzhiyun 	return 0;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun #endif
54*4882a593Smuzhiyun 
reset_cpu(unsigned long ignored)55*4882a593Smuzhiyun void reset_cpu(unsigned long ignored)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun 	/* Address error with SR.BL=1 first. */
58*4882a593Smuzhiyun 	trigger_address_error();
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	while (1)
61*4882a593Smuzhiyun 		;
62*4882a593Smuzhiyun }
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