1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Test-related constants for sandbox 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2014 Google, Inc 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_TEST_H 10*4882a593Smuzhiyun #define __ASM_TEST_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* The sandbox driver always permits an I2C device with this address */ 13*4882a593Smuzhiyun #define SANDBOX_I2C_TEST_ADDR 0x59 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define SANDBOX_PCI_VENDOR_ID 0x1234 16*4882a593Smuzhiyun #define SANDBOX_PCI_DEVICE_ID 0x5678 17*4882a593Smuzhiyun #define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM 18*4882a593Smuzhiyun #define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define SANDBOX_CLK_RATE 32768 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* System controller driver data */ 23*4882a593Smuzhiyun enum { 24*4882a593Smuzhiyun SYSCON0 = 32, 25*4882a593Smuzhiyun SYSCON1, 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun SYSCON_COUNT 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /** 31*4882a593Smuzhiyun * sandbox_i2c_set_test_mode() - set test mode for running unit tests 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun * See sandbox_i2c_xfer() for the behaviour changes. 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * @bus: sandbox I2C bus to adjust 36*4882a593Smuzhiyun * @test_mode: true to select test mode, false to run normally 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun void sandbox_i2c_set_test_mode(struct udevice *bus, bool test_mode); 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun enum sandbox_i2c_eeprom_test_mode { 41*4882a593Smuzhiyun SIE_TEST_MODE_NONE, 42*4882a593Smuzhiyun /* Permits read/write of only one byte per I2C transaction */ 43*4882a593Smuzhiyun SIE_TEST_MODE_SINGLE_BYTE, 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev, 47*4882a593Smuzhiyun enum sandbox_i2c_eeprom_test_mode mode); 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len); 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * sandbox_timer_add_offset() 53*4882a593Smuzhiyun * 54*4882a593Smuzhiyun * Allow tests to add to the time reported through lib/time.c functions 55*4882a593Smuzhiyun * offset: number of milliseconds to advance the system time 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun void sandbox_timer_add_offset(unsigned long offset); 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /** 60*4882a593Smuzhiyun * sandbox_i2c_rtc_set_offset() - set the time offset from system/base time 61*4882a593Smuzhiyun * 62*4882a593Smuzhiyun * @dev: RTC device to adjust 63*4882a593Smuzhiyun * @use_system_time: true to use system time, false to use @base_time 64*4882a593Smuzhiyun * @offset: RTC offset from current system/base time (-1 for no 65*4882a593Smuzhiyun * change) 66*4882a593Smuzhiyun * @return old value of RTC offset 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun long sandbox_i2c_rtc_set_offset(struct udevice *dev, bool use_system_time, 69*4882a593Smuzhiyun int offset); 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /** 72*4882a593Smuzhiyun * sandbox_i2c_rtc_get_set_base_time() - get and set the base time 73*4882a593Smuzhiyun * 74*4882a593Smuzhiyun * @dev: RTC device to adjust 75*4882a593Smuzhiyun * @base_time: New base system time (set to -1 for no change) 76*4882a593Smuzhiyun * @return old base time 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun long sandbox_i2c_rtc_get_set_base_time(struct udevice *dev, long base_time); 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun int sandbox_usb_keyb_add_string(struct udevice *dev, const char *str); 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /** 83*4882a593Smuzhiyun * sandbox_osd_get_mem() - get the internal memory of a sandbox OSD 84*4882a593Smuzhiyun * 85*4882a593Smuzhiyun * @dev: OSD device for which to access the internal memory for 86*4882a593Smuzhiyun * @buf: pointer to buffer to receive the OSD memory data 87*4882a593Smuzhiyun * @buflen: length of buffer in bytes 88*4882a593Smuzhiyun */ 89*4882a593Smuzhiyun int sandbox_osd_get_mem(struct udevice *dev, u8 *buf, size_t buflen); 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /** 92*4882a593Smuzhiyun * sandbox_pwm_get_config() - get the PWM config for a channel 93*4882a593Smuzhiyun * 94*4882a593Smuzhiyun * @dev: Device to check 95*4882a593Smuzhiyun * @channel: Channel number to check 96*4882a593Smuzhiyun * @period_ns: Period of the PWM in nanoseconds 97*4882a593Smuzhiyun * @duty_ns: Current duty cycle of the PWM in nanoseconds 98*4882a593Smuzhiyun * @enable: true if the PWM is enabled 99*4882a593Smuzhiyun * @polarity: true if the PWM polarity is active high 100*4882a593Smuzhiyun * @return 0 if OK, -ENOSPC if the PWM number is invalid 101*4882a593Smuzhiyun */ 102*4882a593Smuzhiyun int sandbox_pwm_get_config(struct udevice *dev, uint channel, uint *period_nsp, 103*4882a593Smuzhiyun uint *duty_nsp, bool *enablep, bool *polarityp); 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /** 106*4882a593Smuzhiyun * sandbox_sf_set_block_protect() - Set the BP bits of the status register 107*4882a593Smuzhiyun * 108*4882a593Smuzhiyun * @dev: Device to update 109*4882a593Smuzhiyun * @bp_mask: BP bits to set (bits 2:0, so a value of 0 to 7) 110*4882a593Smuzhiyun */ 111*4882a593Smuzhiyun void sandbox_sf_set_block_protect(struct udevice *dev, int bp_mask); 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #endif 114