1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 5*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by 6*4882a593Smuzhiyun * the Free Software Foundation; either version 2 of the License, or 7*4882a593Smuzhiyun * (at your option) any later version. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 10*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*4882a593Smuzhiyun * GNU General Public License for more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License 15*4882a593Smuzhiyun * along with this program. If not, see <http://www.gnu.org/licenses/>. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef __DTS_HISTB_CLOCK_H 19*4882a593Smuzhiyun #define __DTS_HISTB_CLOCK_H 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* clocks provided by core CRG */ 22*4882a593Smuzhiyun #define HISTB_OSC_CLK 0 23*4882a593Smuzhiyun #define HISTB_APB_CLK 1 24*4882a593Smuzhiyun #define HISTB_AHB_CLK 2 25*4882a593Smuzhiyun #define HISTB_UART1_CLK 3 26*4882a593Smuzhiyun #define HISTB_UART2_CLK 4 27*4882a593Smuzhiyun #define HISTB_UART3_CLK 5 28*4882a593Smuzhiyun #define HISTB_I2C0_CLK 6 29*4882a593Smuzhiyun #define HISTB_I2C1_CLK 7 30*4882a593Smuzhiyun #define HISTB_I2C2_CLK 8 31*4882a593Smuzhiyun #define HISTB_I2C3_CLK 9 32*4882a593Smuzhiyun #define HISTB_I2C4_CLK 10 33*4882a593Smuzhiyun #define HISTB_I2C5_CLK 11 34*4882a593Smuzhiyun #define HISTB_SPI0_CLK 12 35*4882a593Smuzhiyun #define HISTB_SPI1_CLK 13 36*4882a593Smuzhiyun #define HISTB_SPI2_CLK 14 37*4882a593Smuzhiyun #define HISTB_SCI_CLK 15 38*4882a593Smuzhiyun #define HISTB_FMC_CLK 16 39*4882a593Smuzhiyun #define HISTB_MMC_BIU_CLK 17 40*4882a593Smuzhiyun #define HISTB_MMC_CIU_CLK 18 41*4882a593Smuzhiyun #define HISTB_MMC_DRV_CLK 19 42*4882a593Smuzhiyun #define HISTB_MMC_SAMPLE_CLK 20 43*4882a593Smuzhiyun #define HISTB_SDIO0_BIU_CLK 21 44*4882a593Smuzhiyun #define HISTB_SDIO0_CIU_CLK 22 45*4882a593Smuzhiyun #define HISTB_SDIO0_DRV_CLK 23 46*4882a593Smuzhiyun #define HISTB_SDIO0_SAMPLE_CLK 24 47*4882a593Smuzhiyun #define HISTB_PCIE_AUX_CLK 25 48*4882a593Smuzhiyun #define HISTB_PCIE_PIPE_CLK 26 49*4882a593Smuzhiyun #define HISTB_PCIE_SYS_CLK 27 50*4882a593Smuzhiyun #define HISTB_PCIE_BUS_CLK 28 51*4882a593Smuzhiyun #define HISTB_ETH0_MAC_CLK 29 52*4882a593Smuzhiyun #define HISTB_ETH0_MACIF_CLK 30 53*4882a593Smuzhiyun #define HISTB_ETH1_MAC_CLK 31 54*4882a593Smuzhiyun #define HISTB_ETH1_MACIF_CLK 32 55*4882a593Smuzhiyun #define HISTB_COMBPHY1_CLK 33 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* clocks provided by mcu CRG */ 59*4882a593Smuzhiyun #define HISTB_MCE_CLK 1 60*4882a593Smuzhiyun #define HISTB_IR_CLK 2 61*4882a593Smuzhiyun #define HISTB_TIMER01_CLK 3 62*4882a593Smuzhiyun #define HISTB_LEDC_CLK 4 63*4882a593Smuzhiyun #define HISTB_UART0_CLK 5 64*4882a593Smuzhiyun #define HISTB_LSADC_CLK 6 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #endif /* __DTS_HISTB_CLOCK_H */ 67