1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 3*4882a593Smuzhiyun * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 4*4882a593Smuzhiyun * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de> 5*4882a593Smuzhiyun * Copyright Freescale Semiconductor, Inc. 2004, 2006. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include <config.h> 11*4882a593Smuzhiyun#include <ppc_asm.tmpl> 12*4882a593Smuzhiyun#include <ppc_defs.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun#include <asm/cache.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun/*------------------------------------------------------------------------------- */ 17*4882a593Smuzhiyun/* Function: ppcDcbf */ 18*4882a593Smuzhiyun/* Description: Data Cache block flush */ 19*4882a593Smuzhiyun/* Input: r3 = effective address */ 20*4882a593Smuzhiyun/* Output: none. */ 21*4882a593Smuzhiyun/*------------------------------------------------------------------------------- */ 22*4882a593Smuzhiyun .globl ppcDcbf 23*4882a593SmuzhiyunppcDcbf: 24*4882a593Smuzhiyun dcbf r0,r3 25*4882a593Smuzhiyun blr 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun/*------------------------------------------------------------------------------- */ 28*4882a593Smuzhiyun/* Function: ppcDcbi */ 29*4882a593Smuzhiyun/* Description: Data Cache block Invalidate */ 30*4882a593Smuzhiyun/* Input: r3 = effective address */ 31*4882a593Smuzhiyun/* Output: none. */ 32*4882a593Smuzhiyun/*------------------------------------------------------------------------------- */ 33*4882a593Smuzhiyun .globl ppcDcbi 34*4882a593SmuzhiyunppcDcbi: 35*4882a593Smuzhiyun dcbi r0,r3 36*4882a593Smuzhiyun blr 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun/*-------------------------------------------------------------------------- 39*4882a593Smuzhiyun * Function: ppcDcbz 40*4882a593Smuzhiyun * Description: Data Cache block zero. 41*4882a593Smuzhiyun * Input: r3 = effective address 42*4882a593Smuzhiyun * Output: none. 43*4882a593Smuzhiyun *-------------------------------------------------------------------------- */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun .globl ppcDcbz 46*4882a593SmuzhiyunppcDcbz: 47*4882a593Smuzhiyun dcbz r0,r3 48*4882a593Smuzhiyun blr 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun/*------------------------------------------------------------------------------- */ 51*4882a593Smuzhiyun/* Function: ppcSync */ 52*4882a593Smuzhiyun/* Description: Processor Synchronize */ 53*4882a593Smuzhiyun/* Input: none. */ 54*4882a593Smuzhiyun/* Output: none. */ 55*4882a593Smuzhiyun/*------------------------------------------------------------------------------- */ 56*4882a593Smuzhiyun .globl ppcSync 57*4882a593SmuzhiyunppcSync: 58*4882a593Smuzhiyun sync 59*4882a593Smuzhiyun blr 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun/* 62*4882a593Smuzhiyun * Write any modified data cache blocks out to memory and invalidate them. 63*4882a593Smuzhiyun * Does not invalidate the corresponding instruction cache blocks. 64*4882a593Smuzhiyun * 65*4882a593Smuzhiyun * flush_dcache_range(unsigned long start, unsigned long stop) 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun_GLOBAL(flush_dcache_range) 68*4882a593Smuzhiyun#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) 69*4882a593Smuzhiyun li r5,L1_CACHE_BYTES-1 70*4882a593Smuzhiyun andc r3,r3,r5 71*4882a593Smuzhiyun subf r4,r3,r4 72*4882a593Smuzhiyun add r4,r4,r5 73*4882a593Smuzhiyun srwi. r4,r4,L1_CACHE_SHIFT 74*4882a593Smuzhiyun beqlr 75*4882a593Smuzhiyun mtctr r4 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun1: dcbf 0,r3 78*4882a593Smuzhiyun addi r3,r3,L1_CACHE_BYTES 79*4882a593Smuzhiyun bdnz 1b 80*4882a593Smuzhiyun sync /* wait for dcbst's to get to ram */ 81*4882a593Smuzhiyun#endif 82*4882a593Smuzhiyun blr 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun/* 85*4882a593Smuzhiyun * Like above, but invalidate the D-cache. This is used by the 8xx 86*4882a593Smuzhiyun * to invalidate the cache so the PPC core doesn't get stale data 87*4882a593Smuzhiyun * from the CPM (no cache snooping here :-). 88*4882a593Smuzhiyun * 89*4882a593Smuzhiyun * invalidate_dcache_range(unsigned long start, unsigned long stop) 90*4882a593Smuzhiyun */ 91*4882a593Smuzhiyun_GLOBAL(invalidate_dcache_range) 92*4882a593Smuzhiyun#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) 93*4882a593Smuzhiyun li r5,L1_CACHE_BYTES-1 94*4882a593Smuzhiyun andc r3,r3,r5 95*4882a593Smuzhiyun subf r4,r3,r4 96*4882a593Smuzhiyun add r4,r4,r5 97*4882a593Smuzhiyun srwi. r4,r4,L1_CACHE_SHIFT 98*4882a593Smuzhiyun beqlr 99*4882a593Smuzhiyun mtctr r4 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun sync 102*4882a593Smuzhiyun1: dcbi 0,r3 103*4882a593Smuzhiyun addi r3,r3,L1_CACHE_BYTES 104*4882a593Smuzhiyun bdnz 1b 105*4882a593Smuzhiyun sync /* wait for dcbi's to get to ram */ 106*4882a593Smuzhiyun#endif 107*4882a593Smuzhiyun blr 108*4882a593Smuzhiyun 109