1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2002 3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun #include <asm/cache.h> 10*4882a593Smuzhiyun #include <watchdog.h> 11*4882a593Smuzhiyun flush_cache(ulong start_addr,ulong size)12*4882a593Smuzhiyunvoid flush_cache(ulong start_addr, ulong size) 13*4882a593Smuzhiyun { 14*4882a593Smuzhiyun #ifndef CONFIG_5xx 15*4882a593Smuzhiyun ulong addr, start, end; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1); 18*4882a593Smuzhiyun end = start_addr + size - 1; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun for (addr = start; (addr <= end) && (addr >= start); 21*4882a593Smuzhiyun addr += CONFIG_SYS_CACHELINE_SIZE) { 22*4882a593Smuzhiyun asm volatile("dcbst 0,%0" : : "r" (addr) : "memory"); 23*4882a593Smuzhiyun WATCHDOG_RESET(); 24*4882a593Smuzhiyun } 25*4882a593Smuzhiyun /* wait for all dcbst to complete on bus */ 26*4882a593Smuzhiyun asm volatile("sync" : : : "memory"); 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun for (addr = start; (addr <= end) && (addr >= start); 29*4882a593Smuzhiyun addr += CONFIG_SYS_CACHELINE_SIZE) { 30*4882a593Smuzhiyun asm volatile("icbi 0,%0" : : "r" (addr) : "memory"); 31*4882a593Smuzhiyun WATCHDOG_RESET(); 32*4882a593Smuzhiyun } 33*4882a593Smuzhiyun asm volatile("sync" : : : "memory"); 34*4882a593Smuzhiyun /* flush prefetch queue */ 35*4882a593Smuzhiyun asm volatile("isync" : : : "memory"); 36*4882a593Smuzhiyun #endif 37*4882a593Smuzhiyun } 38