1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2008 3*4882a593Smuzhiyun * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com 4*4882a593Smuzhiyun * This work has been supported by: QTechnology http://qtec.com/ 5*4882a593Smuzhiyun * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef XILINX_IRQ_H 9*4882a593Smuzhiyun #define XILINX_IRQ_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define intc XPAR_INTC_0_BASEADDR 12*4882a593Smuzhiyun #define ISR (intc + (0 * 4)) /* Interrupt Status Register */ 13*4882a593Smuzhiyun #define IPR (intc + (1 * 4)) /* Interrupt Pending Register */ 14*4882a593Smuzhiyun #define IER (intc + (2 * 4)) /* Interrupt Enable Register */ 15*4882a593Smuzhiyun #define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */ 16*4882a593Smuzhiyun #define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */ 17*4882a593Smuzhiyun #define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */ 18*4882a593Smuzhiyun #define IVR (intc + (6 * 4)) /* Interrupt Vector Register */ 19*4882a593Smuzhiyun #define MER (intc + (7 * 4)) /* Master Enable Register */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define IRQ_MASK(irq) (1 << (irq & 0x1f)) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #endif 26