1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Freescale non-CPM SPI Controller 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2008 Qstreams Networks, Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _ASM_MPC8XXX_SPI_H_ 10*4882a593Smuzhiyun #define _ASM_MPC8XXX_SPI_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <asm/types.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #if defined(CONFIG_MPC8308) || \ 15*4882a593Smuzhiyun defined(CONFIG_MPC8313) || \ 16*4882a593Smuzhiyun defined(CONFIG_MPC8315) || \ 17*4882a593Smuzhiyun defined(CONFIG_MPC834x) || \ 18*4882a593Smuzhiyun defined(CONFIG_MPC837x) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun typedef struct spi8xxx { 21*4882a593Smuzhiyun u8 res0[0x20]; /* 0x0-0x01f reserved */ 22*4882a593Smuzhiyun u32 mode; /* mode register */ 23*4882a593Smuzhiyun u32 event; /* event register */ 24*4882a593Smuzhiyun u32 mask; /* mask register */ 25*4882a593Smuzhiyun u32 com; /* command register */ 26*4882a593Smuzhiyun u32 tx; /* transmit register */ 27*4882a593Smuzhiyun u32 rx; /* receive register */ 28*4882a593Smuzhiyun u8 res1[0xFC8]; /* fill up to 0x1000 */ 29*4882a593Smuzhiyun } spi8xxx_t; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #endif 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #endif /* _ASM_MPC8XXX_SPI_H_ */ 34