1*4882a593Smuzhiyun /* originally from linux source.
2*4882a593Smuzhiyun * removed the dependencies on CONFIG_ values
3*4882a593Smuzhiyun * removed virt_to_phys stuff (and in fact everything surrounded by #if __KERNEL__)
4*4882a593Smuzhiyun * Modified By Rob Taylor, Flying Pig Systems, 2000
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef _PPC_IO_H
8*4882a593Smuzhiyun #define _PPC_IO_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <asm/byteorder.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #ifdef CONFIG_ADDR_MAP
13*4882a593Smuzhiyun #include <addr_map.h>
14*4882a593Smuzhiyun #endif
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define SIO_CONFIG_RA 0x398
17*4882a593Smuzhiyun #define SIO_CONFIG_RD 0x399
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #ifndef _IO_BASE
20*4882a593Smuzhiyun #define _IO_BASE 0
21*4882a593Smuzhiyun #endif
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define readb(addr) in_8((volatile u8 *)(addr))
24*4882a593Smuzhiyun #define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
25*4882a593Smuzhiyun #if !defined(__BIG_ENDIAN)
26*4882a593Smuzhiyun #define readw(addr) (*(volatile u16 *) (addr))
27*4882a593Smuzhiyun #define readl(addr) (*(volatile u32 *) (addr))
28*4882a593Smuzhiyun #define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
29*4882a593Smuzhiyun #define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
30*4882a593Smuzhiyun #else
31*4882a593Smuzhiyun #define readw(addr) in_le16((volatile u16 *)(addr))
32*4882a593Smuzhiyun #define readl(addr) in_le32((volatile u32 *)(addr))
33*4882a593Smuzhiyun #define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
34*4882a593Smuzhiyun #define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
35*4882a593Smuzhiyun #endif
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /*
38*4882a593Smuzhiyun * The insw/outsw/insl/outsl macros don't do byte-swapping.
39*4882a593Smuzhiyun * They are only used in practice for transferring buffers which
40*4882a593Smuzhiyun * are arrays of bytes, and byte-swapping is not appropriate in
41*4882a593Smuzhiyun * that case. - paulus
42*4882a593Smuzhiyun */
43*4882a593Smuzhiyun #define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
44*4882a593Smuzhiyun #define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
45*4882a593Smuzhiyun #define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
46*4882a593Smuzhiyun #define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
47*4882a593Smuzhiyun #define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
48*4882a593Smuzhiyun #define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define inb(port) in_8((u8 *)((port)+_IO_BASE))
51*4882a593Smuzhiyun #define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
52*4882a593Smuzhiyun #if !defined(__BIG_ENDIAN)
53*4882a593Smuzhiyun #define inw(port) in_be16((u16 *)((port)+_IO_BASE))
54*4882a593Smuzhiyun #define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
55*4882a593Smuzhiyun #define inl(port) in_be32((u32 *)((port)+_IO_BASE))
56*4882a593Smuzhiyun #define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
57*4882a593Smuzhiyun #else
58*4882a593Smuzhiyun #define inw(port) in_le16((u16 *)((port)+_IO_BASE))
59*4882a593Smuzhiyun #define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
60*4882a593Smuzhiyun #define inl(port) in_le32((u32 *)((port)+_IO_BASE))
61*4882a593Smuzhiyun #define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
62*4882a593Smuzhiyun #endif
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define inb_p(port) in_8((u8 *)((port)+_IO_BASE))
65*4882a593Smuzhiyun #define outb_p(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
66*4882a593Smuzhiyun #define inw_p(port) in_le16((u16 *)((port)+_IO_BASE))
67*4882a593Smuzhiyun #define outw_p(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
68*4882a593Smuzhiyun #define inl_p(port) in_le32((u32 *)((port)+_IO_BASE))
69*4882a593Smuzhiyun #define outl_p(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun extern void _insb(volatile u8 *port, void *buf, int ns);
72*4882a593Smuzhiyun extern void _outsb(volatile u8 *port, const void *buf, int ns);
73*4882a593Smuzhiyun extern void _insw(volatile u16 *port, void *buf, int ns);
74*4882a593Smuzhiyun extern void _outsw(volatile u16 *port, const void *buf, int ns);
75*4882a593Smuzhiyun extern void _insl(volatile u32 *port, void *buf, int nl);
76*4882a593Smuzhiyun extern void _outsl(volatile u32 *port, const void *buf, int nl);
77*4882a593Smuzhiyun extern void _insw_ns(volatile u16 *port, void *buf, int ns);
78*4882a593Smuzhiyun extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
79*4882a593Smuzhiyun extern void _insl_ns(volatile u32 *port, void *buf, int nl);
80*4882a593Smuzhiyun extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun * The *_ns versions below don't do byte-swapping.
84*4882a593Smuzhiyun * Neither do the standard versions now, these are just here
85*4882a593Smuzhiyun * for older code.
86*4882a593Smuzhiyun */
87*4882a593Smuzhiyun #define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
88*4882a593Smuzhiyun #define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
89*4882a593Smuzhiyun #define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
90*4882a593Smuzhiyun #define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun #define IO_SPACE_LIMIT ~0
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun #define memset_io(a,b,c) memset((void *)(a),(b),(c))
96*4882a593Smuzhiyun #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
97*4882a593Smuzhiyun #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /*
100*4882a593Smuzhiyun * Enforce In-order Execution of I/O:
101*4882a593Smuzhiyun * Acts as a barrier to ensure all previous I/O accesses have
102*4882a593Smuzhiyun * completed before any further ones are issued.
103*4882a593Smuzhiyun */
eieio(void)104*4882a593Smuzhiyun static inline void eieio(void)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun __asm__ __volatile__ ("eieio" : : : "memory");
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
sync(void)109*4882a593Smuzhiyun static inline void sync(void)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun __asm__ __volatile__ ("sync" : : : "memory");
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
isync(void)114*4882a593Smuzhiyun static inline void isync(void)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun __asm__ __volatile__ ("isync" : : : "memory");
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* Enforce in-order execution of data I/O.
120*4882a593Smuzhiyun * No distinction between read/write on PPC; use eieio for all three.
121*4882a593Smuzhiyun */
122*4882a593Smuzhiyun #define iobarrier_rw() eieio()
123*4882a593Smuzhiyun #define iobarrier_r() eieio()
124*4882a593Smuzhiyun #define iobarrier_w() eieio()
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun #define mb() sync()
127*4882a593Smuzhiyun #define isb() isync()
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /*
130*4882a593Smuzhiyun * Non ordered and non-swapping "raw" accessors
131*4882a593Smuzhiyun */
132*4882a593Smuzhiyun #define PCI_FIX_ADDR(addr) (addr)
133*4882a593Smuzhiyun
__raw_readb(const volatile void __iomem * addr)134*4882a593Smuzhiyun static inline unsigned char __raw_readb(const volatile void __iomem *addr)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
137*4882a593Smuzhiyun }
__raw_readw(const volatile void __iomem * addr)138*4882a593Smuzhiyun static inline unsigned short __raw_readw(const volatile void __iomem *addr)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
141*4882a593Smuzhiyun }
__raw_readl(const volatile void __iomem * addr)142*4882a593Smuzhiyun static inline unsigned int __raw_readl(const volatile void __iomem *addr)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
145*4882a593Smuzhiyun }
__raw_writeb(unsigned char v,volatile void __iomem * addr)146*4882a593Smuzhiyun static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun *(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
149*4882a593Smuzhiyun }
__raw_writew(unsigned short v,volatile void __iomem * addr)150*4882a593Smuzhiyun static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun *(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
153*4882a593Smuzhiyun }
__raw_writel(unsigned int v,volatile void __iomem * addr)154*4882a593Smuzhiyun static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun *(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun /*
160*4882a593Smuzhiyun * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
161*4882a593Smuzhiyun *
162*4882a593Smuzhiyun * Read operations have additional twi & isync to make sure the read
163*4882a593Smuzhiyun * is actually performed (i.e. the data has come back) before we start
164*4882a593Smuzhiyun * executing any following instructions.
165*4882a593Smuzhiyun */
in_8(const volatile unsigned char __iomem * addr)166*4882a593Smuzhiyun static inline u8 in_8(const volatile unsigned char __iomem *addr)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun u8 ret;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun __asm__ __volatile__(
171*4882a593Smuzhiyun "sync; lbz%U1%X1 %0,%1;\n"
172*4882a593Smuzhiyun "twi 0,%0,0;\n"
173*4882a593Smuzhiyun "isync" : "=r" (ret) : "m" (*addr));
174*4882a593Smuzhiyun return ret;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
out_8(volatile unsigned char __iomem * addr,u8 val)177*4882a593Smuzhiyun static inline void out_8(volatile unsigned char __iomem *addr, u8 val)
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun __asm__ __volatile__("sync;\n"
180*4882a593Smuzhiyun "stb%U0%X0 %1,%0;\n"
181*4882a593Smuzhiyun : "=m" (*addr)
182*4882a593Smuzhiyun : "r" (val));
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
in_le16(const volatile unsigned short __iomem * addr)185*4882a593Smuzhiyun static inline u16 in_le16(const volatile unsigned short __iomem *addr)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun u16 ret;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun __asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
190*4882a593Smuzhiyun "twi 0,%0,0;\n"
191*4882a593Smuzhiyun "isync" : "=r" (ret) :
192*4882a593Smuzhiyun "r" (addr), "m" (*addr));
193*4882a593Smuzhiyun return ret;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
in_be16(const volatile unsigned short __iomem * addr)196*4882a593Smuzhiyun static inline u16 in_be16(const volatile unsigned short __iomem *addr)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun u16 ret;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
201*4882a593Smuzhiyun "twi 0,%0,0;\n"
202*4882a593Smuzhiyun "isync" : "=r" (ret) : "m" (*addr));
203*4882a593Smuzhiyun return ret;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun
out_le16(volatile unsigned short __iomem * addr,u16 val)206*4882a593Smuzhiyun static inline void out_le16(volatile unsigned short __iomem *addr, u16 val)
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
209*4882a593Smuzhiyun "r" (val), "r" (addr));
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
out_be16(volatile unsigned short __iomem * addr,u16 val)212*4882a593Smuzhiyun static inline void out_be16(volatile unsigned short __iomem *addr, u16 val)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
in_le32(const volatile unsigned __iomem * addr)217*4882a593Smuzhiyun static inline u32 in_le32(const volatile unsigned __iomem *addr)
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun u32 ret;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun __asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
222*4882a593Smuzhiyun "twi 0,%0,0;\n"
223*4882a593Smuzhiyun "isync" : "=r" (ret) :
224*4882a593Smuzhiyun "r" (addr), "m" (*addr));
225*4882a593Smuzhiyun return ret;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
in_be32(const volatile unsigned __iomem * addr)228*4882a593Smuzhiyun static inline u32 in_be32(const volatile unsigned __iomem *addr)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun u32 ret;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
233*4882a593Smuzhiyun "twi 0,%0,0;\n"
234*4882a593Smuzhiyun "isync" : "=r" (ret) : "m" (*addr));
235*4882a593Smuzhiyun return ret;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun
out_le32(volatile unsigned __iomem * addr,u32 val)238*4882a593Smuzhiyun static inline void out_le32(volatile unsigned __iomem *addr, u32 val)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
241*4882a593Smuzhiyun "r" (val), "r" (addr));
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun
out_be32(volatile unsigned __iomem * addr,u32 val)244*4882a593Smuzhiyun static inline void out_be32(volatile unsigned __iomem *addr, u32 val)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun /* Clear and set bits in one shot. These macros can be used to clear and
250*4882a593Smuzhiyun * set multiple bits in a register using a single call. These macros can
251*4882a593Smuzhiyun * also be used to set a multiple-bit bit pattern using a mask, by
252*4882a593Smuzhiyun * specifying the mask in the 'clear' parameter and the new bit pattern
253*4882a593Smuzhiyun * in the 'set' parameter.
254*4882a593Smuzhiyun */
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun #define clrbits(type, addr, clear) \
257*4882a593Smuzhiyun out_##type((addr), in_##type(addr) & ~(clear))
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun #define setbits(type, addr, set) \
260*4882a593Smuzhiyun out_##type((addr), in_##type(addr) | (set))
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun #define clrsetbits(type, addr, clear, set) \
263*4882a593Smuzhiyun out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun #define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
266*4882a593Smuzhiyun #define setbits_be32(addr, set) setbits(be32, addr, set)
267*4882a593Smuzhiyun #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun #define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
270*4882a593Smuzhiyun #define setbits_le32(addr, set) setbits(le32, addr, set)
271*4882a593Smuzhiyun #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun #define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
274*4882a593Smuzhiyun #define setbits_be16(addr, set) setbits(be16, addr, set)
275*4882a593Smuzhiyun #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun #define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
278*4882a593Smuzhiyun #define setbits_le16(addr, set) setbits(le16, addr, set)
279*4882a593Smuzhiyun #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun #define clrbits_8(addr, clear) clrbits(8, addr, clear)
282*4882a593Smuzhiyun #define setbits_8(addr, set) setbits(8, addr, set)
283*4882a593Smuzhiyun #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun /*
286*4882a593Smuzhiyun * Given a physical address and a length, return a virtual address
287*4882a593Smuzhiyun * that can be used to access the memory range with the caching
288*4882a593Smuzhiyun * properties specified by "flags".
289*4882a593Smuzhiyun */
290*4882a593Smuzhiyun #define MAP_NOCACHE (0)
291*4882a593Smuzhiyun #define MAP_WRCOMBINE (0)
292*4882a593Smuzhiyun #define MAP_WRBACK (0)
293*4882a593Smuzhiyun #define MAP_WRTHROUGH (0)
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun static inline void *
map_physmem(phys_addr_t paddr,unsigned long len,unsigned long flags)296*4882a593Smuzhiyun map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
297*4882a593Smuzhiyun {
298*4882a593Smuzhiyun #ifdef CONFIG_ADDR_MAP
299*4882a593Smuzhiyun return addrmap_phys_to_virt(paddr);
300*4882a593Smuzhiyun #else
301*4882a593Smuzhiyun return (void *)((unsigned long)paddr);
302*4882a593Smuzhiyun #endif
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun /*
306*4882a593Smuzhiyun * Take down a mapping set up by map_physmem().
307*4882a593Smuzhiyun */
unmap_physmem(void * vaddr,unsigned long flags)308*4882a593Smuzhiyun static inline void unmap_physmem(void *vaddr, unsigned long flags)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
virt_to_phys(void * vaddr)313*4882a593Smuzhiyun static inline phys_addr_t virt_to_phys(void * vaddr)
314*4882a593Smuzhiyun {
315*4882a593Smuzhiyun #ifdef CONFIG_ADDR_MAP
316*4882a593Smuzhiyun return addrmap_virt_to_phys(vaddr);
317*4882a593Smuzhiyun #else
318*4882a593Smuzhiyun return (phys_addr_t)((unsigned long)vaddr);
319*4882a593Smuzhiyun #endif
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun #endif
323