1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Freescale I2C Controller 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2006 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>, 7*4882a593Smuzhiyun * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com), 8*4882a593Smuzhiyun * and Jeff Brown. 9*4882a593Smuzhiyun * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef _ASM_FSL_I2C_H_ 15*4882a593Smuzhiyun #define _ASM_FSL_I2C_H_ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <asm/types.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun typedef struct fsl_i2c_base { 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun u8 adr; /* I2C slave address */ 22*4882a593Smuzhiyun u8 res0[3]; 23*4882a593Smuzhiyun #define I2C_ADR 0xFE 24*4882a593Smuzhiyun #define I2C_ADR_SHIFT 1 25*4882a593Smuzhiyun #define I2C_ADR_RES ~(I2C_ADR) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun u8 fdr; /* I2C frequency divider register */ 28*4882a593Smuzhiyun u8 res1[3]; 29*4882a593Smuzhiyun #define IC2_FDR 0x3F 30*4882a593Smuzhiyun #define IC2_FDR_SHIFT 0 31*4882a593Smuzhiyun #define IC2_FDR_RES ~(IC2_FDR) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun u8 cr; /* I2C control redister */ 34*4882a593Smuzhiyun u8 res2[3]; 35*4882a593Smuzhiyun #define I2C_CR_MEN 0x80 36*4882a593Smuzhiyun #define I2C_CR_MIEN 0x40 37*4882a593Smuzhiyun #define I2C_CR_MSTA 0x20 38*4882a593Smuzhiyun #define I2C_CR_MTX 0x10 39*4882a593Smuzhiyun #define I2C_CR_TXAK 0x08 40*4882a593Smuzhiyun #define I2C_CR_RSTA 0x04 41*4882a593Smuzhiyun #define I2C_CR_BIT6 0x02 /* required for workaround A004447 */ 42*4882a593Smuzhiyun #define I2C_CR_BCST 0x01 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun u8 sr; /* I2C status register */ 45*4882a593Smuzhiyun u8 res3[3]; 46*4882a593Smuzhiyun #define I2C_SR_MCF 0x80 47*4882a593Smuzhiyun #define I2C_SR_MAAS 0x40 48*4882a593Smuzhiyun #define I2C_SR_MBB 0x20 49*4882a593Smuzhiyun #define I2C_SR_MAL 0x10 50*4882a593Smuzhiyun #define I2C_SR_BCSTM 0x08 51*4882a593Smuzhiyun #define I2C_SR_SRW 0x04 52*4882a593Smuzhiyun #define I2C_SR_MIF 0x02 53*4882a593Smuzhiyun #define I2C_SR_RXAK 0x01 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun u8 dr; /* I2C data register */ 56*4882a593Smuzhiyun u8 res4[3]; 57*4882a593Smuzhiyun #define I2C_DR 0xFF 58*4882a593Smuzhiyun #define I2C_DR_SHIFT 0 59*4882a593Smuzhiyun #define I2C_DR_RES ~(I2C_DR) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun u8 dfsrr; /* I2C digital filter sampling rate register */ 62*4882a593Smuzhiyun u8 res5[3]; 63*4882a593Smuzhiyun #define I2C_DFSRR 0x3F 64*4882a593Smuzhiyun #define I2C_DFSRR_SHIFT 0 65*4882a593Smuzhiyun #define I2C_DFSRR_RES ~(I2C_DR) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Fill out the reserved block */ 68*4882a593Smuzhiyun u8 res6[0xE8]; 69*4882a593Smuzhiyun } fsl_i2c_t; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #ifdef CONFIG_DM_I2C 72*4882a593Smuzhiyun struct fsl_i2c_dev { 73*4882a593Smuzhiyun struct fsl_i2c_base __iomem *base; /* register base */ 74*4882a593Smuzhiyun u32 i2c_clk; 75*4882a593Smuzhiyun u32 index; 76*4882a593Smuzhiyun u8 slaveadd; 77*4882a593Smuzhiyun uint speed; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun #endif 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #endif /* _ASM_I2C_H_ */ 82