1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2000-2004 3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun #include <mpc8xx.h> 10*4882a593Smuzhiyun #include <asm/processor.h> 11*4882a593Smuzhiyun #include <asm/io.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ 17*4882a593Smuzhiyun */ get_clocks(void)18*4882a593Smuzhiyunint get_clocks(void) 19*4882a593Smuzhiyun { 20*4882a593Smuzhiyun uint immr = get_immr(0); /* Return full IMMR contents */ 21*4882a593Smuzhiyun immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000); 22*4882a593Smuzhiyun uint sccr = in_be32(&immap->im_clkrst.car_sccr); 23*4882a593Smuzhiyun uint divider = 1 << (((sccr & SCCR_DFBRG11) >> 11) * 2); 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * If for some reason measuring the gclk frequency won't 27*4882a593Smuzhiyun * work, we return the hardwired value. 28*4882a593Smuzhiyun * (For example, the cogent CMA286-60 CPU module has no 29*4882a593Smuzhiyun * separate oscillator for PITRTCLK) 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun gd->cpu_clk = CONFIG_8xx_GCLK_FREQ; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun if ((sccr & SCCR_EBDF11) == 0) { 34*4882a593Smuzhiyun /* No Bus Divider active */ 35*4882a593Smuzhiyun gd->bus_clk = gd->cpu_clk; 36*4882a593Smuzhiyun } else { 37*4882a593Smuzhiyun /* The MPC8xx has only one BDF: half clock speed */ 38*4882a593Smuzhiyun gd->bus_clk = gd->cpu_clk / 2; 39*4882a593Smuzhiyun } 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun gd->arch.brg_clk = gd->cpu_clk / divider; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun return 0; 44*4882a593Smuzhiyun } 45