1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2017
3*4882a593Smuzhiyun * Christophe Leroy, CS Systemes d'Information, christophe.leroy@c-s.fr
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <asm/processor.h>
10*4882a593Smuzhiyun #include <asm/ppc.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <asm/mmu.h>
13*4882a593Smuzhiyun
icache_status(void)14*4882a593Smuzhiyun int icache_status(void)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun return !!(mfspr(IC_CST) & IDC_ENABLED);
17*4882a593Smuzhiyun }
18*4882a593Smuzhiyun
icache_enable(void)19*4882a593Smuzhiyun void icache_enable(void)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun sync();
22*4882a593Smuzhiyun mtspr(IC_CST, IDC_INVALL);
23*4882a593Smuzhiyun mtspr(IC_CST, IDC_ENABLE);
24*4882a593Smuzhiyun }
25*4882a593Smuzhiyun
icache_disable(void)26*4882a593Smuzhiyun void icache_disable(void)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun sync();
29*4882a593Smuzhiyun mtspr(IC_CST, IDC_DISABLE);
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
dcache_status(void)32*4882a593Smuzhiyun int dcache_status(void)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun return !!(mfspr(IC_CST) & IDC_ENABLED);
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
dcache_enable(void)37*4882a593Smuzhiyun void dcache_enable(void)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun mtspr(MD_CTR, MD_RESETVAL); /* Set cache mode with MMU off */
40*4882a593Smuzhiyun mtspr(DC_CST, IDC_INVALL);
41*4882a593Smuzhiyun mtspr(DC_CST, IDC_ENABLE);
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
dcache_disable(void)44*4882a593Smuzhiyun void dcache_disable(void)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun sync();
47*4882a593Smuzhiyun mtspr(DC_CST, IDC_DISABLE);
48*4882a593Smuzhiyun mtspr(DC_CST, IDC_INVALL);
49*4882a593Smuzhiyun }
50