1*4882a593Smuzhiyunmenu "mpc8xx CPU" 2*4882a593Smuzhiyun depends on MPC8xx 3*4882a593Smuzhiyun 4*4882a593Smuzhiyunconfig SYS_CPU 5*4882a593Smuzhiyun default "mpc8xx" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyunchoice 8*4882a593Smuzhiyun prompt "Target select" 9*4882a593Smuzhiyun optional 10*4882a593Smuzhiyun 11*4882a593Smuzhiyunconfig TARGET_MCR3000 12*4882a593Smuzhiyun bool "Support MCR3000 board from CSSI" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyunendchoice 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunchoice 17*4882a593Smuzhiyun prompt "CPU select" 18*4882a593Smuzhiyun default MPC866 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunconfig MPC866 21*4882a593Smuzhiyun bool "MPC866" 22*4882a593Smuzhiyun 23*4882a593Smuzhiyunconfig MPC885 24*4882a593Smuzhiyun bool "MPC885" 25*4882a593Smuzhiyun 26*4882a593Smuzhiyunendchoice 27*4882a593Smuzhiyun 28*4882a593Smuzhiyunconfig 8xx_GCLK_FREQ 29*4882a593Smuzhiyun int "CPU GCLK Frequency" 30*4882a593Smuzhiyun 31*4882a593Smuzhiyuncomment "Specific commands" 32*4882a593Smuzhiyun 33*4882a593Smuzhiyunconfig CMD_IMMAP 34*4882a593Smuzhiyun bool "Enable various commands to dump IMMR information" 35*4882a593Smuzhiyun help 36*4882a593Smuzhiyun This enables various commands such as: 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun siuinfo - print System Interface Unit (SIU) registers 39*4882a593Smuzhiyun memcinfo - print Memory Controller registers 40*4882a593Smuzhiyun 41*4882a593Smuzhiyuncomment "Configuration Registers" 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunconfig SYS_SIUMCR 44*4882a593Smuzhiyun hex "SIUMCR register" 45*4882a593Smuzhiyun help 46*4882a593Smuzhiyun SIU Module Configuration (11-6) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunconfig SYS_SYPCR 49*4882a593Smuzhiyun hex "SYPCR register" 50*4882a593Smuzhiyun help 51*4882a593Smuzhiyun System Protection Control (11-9) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunconfig SYS_TBSCR 54*4882a593Smuzhiyun hex "TBSCR register" 55*4882a593Smuzhiyun help 56*4882a593Smuzhiyun Time Base Status and Control (11-26) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyunconfig SYS_PISCR 59*4882a593Smuzhiyun hex "PISCR register" 60*4882a593Smuzhiyun help 61*4882a593Smuzhiyun Periodic Interrupt Status and Control (11-31) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyunconfig SYS_PLPRCR_BOOL 64*4882a593Smuzhiyun bool "Customise PLPRCR" 65*4882a593Smuzhiyun 66*4882a593Smuzhiyunconfig SYS_PLPRCR 67*4882a593Smuzhiyun hex "PLPRCR register" 68*4882a593Smuzhiyun depends on SYS_PLPRCR_BOOL 69*4882a593Smuzhiyun help 70*4882a593Smuzhiyun PLL, Low-Power, and Reset Control Register (15-30) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyunconfig SYS_SCCR 73*4882a593Smuzhiyun hex "SCCR register" 74*4882a593Smuzhiyun help 75*4882a593Smuzhiyun System Clock and reset Control Register (15-27) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyunconfig SYS_SCCR_MASK 78*4882a593Smuzhiyun hex "MASK for setting SCCR register" 79*4882a593Smuzhiyun 80*4882a593Smuzhiyunconfig SYS_DER 81*4882a593Smuzhiyun hex "DER register" 82*4882a593Smuzhiyun help 83*4882a593Smuzhiyun Debug Event Register (37-47) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyuncomment "Memory mapping" 86*4882a593Smuzhiyun 87*4882a593Smuzhiyunconfig SYS_BR0_PRELIM 88*4882a593Smuzhiyun hex "Preliminary value for BR0" 89*4882a593Smuzhiyun 90*4882a593Smuzhiyunconfig SYS_OR0_PRELIM 91*4882a593Smuzhiyun hex "Preliminary value for OR0" 92*4882a593Smuzhiyun 93*4882a593Smuzhiyunconfig SYS_BR1_PRELIM_BOOL 94*4882a593Smuzhiyun bool "Define Bank 1" 95*4882a593Smuzhiyun 96*4882a593Smuzhiyunconfig SYS_BR1_PRELIM 97*4882a593Smuzhiyun hex "Preliminary value for BR1" 98*4882a593Smuzhiyun depends on SYS_BR1_PRELIM_BOOL 99*4882a593Smuzhiyun 100*4882a593Smuzhiyunconfig SYS_OR1_PRELIM 101*4882a593Smuzhiyun hex "Preliminary value for OR1" 102*4882a593Smuzhiyun depends on SYS_BR1_PRELIM_BOOL 103*4882a593Smuzhiyun 104*4882a593Smuzhiyunconfig SYS_BR2_PRELIM_BOOL 105*4882a593Smuzhiyun bool "Define Bank 2" 106*4882a593Smuzhiyun 107*4882a593Smuzhiyunconfig SYS_BR2_PRELIM 108*4882a593Smuzhiyun hex "Preliminary value for BR2" 109*4882a593Smuzhiyun depends on SYS_BR2_PRELIM_BOOL 110*4882a593Smuzhiyun 111*4882a593Smuzhiyunconfig SYS_OR2_PRELIM 112*4882a593Smuzhiyun hex "Preliminary value for OR2" 113*4882a593Smuzhiyun depends on SYS_BR2_PRELIM_BOOL 114*4882a593Smuzhiyun 115*4882a593Smuzhiyunconfig SYS_BR3_PRELIM_BOOL 116*4882a593Smuzhiyun bool "Define Bank 3" 117*4882a593Smuzhiyun 118*4882a593Smuzhiyunconfig SYS_BR3_PRELIM 119*4882a593Smuzhiyun hex "Preliminary value for BR3" 120*4882a593Smuzhiyun depends on SYS_BR3_PRELIM_BOOL 121*4882a593Smuzhiyun 122*4882a593Smuzhiyunconfig SYS_OR3_PRELIM 123*4882a593Smuzhiyun hex "Preliminary value for OR3" 124*4882a593Smuzhiyun depends on SYS_BR3_PRELIM_BOOL 125*4882a593Smuzhiyun 126*4882a593Smuzhiyunconfig SYS_BR4_PRELIM_BOOL 127*4882a593Smuzhiyun bool "Define Bank 4" 128*4882a593Smuzhiyun 129*4882a593Smuzhiyunconfig SYS_BR4_PRELIM 130*4882a593Smuzhiyun hex "Preliminary value for BR4" 131*4882a593Smuzhiyun depends on SYS_BR4_PRELIM_BOOL 132*4882a593Smuzhiyun 133*4882a593Smuzhiyunconfig SYS_OR4_PRELIM 134*4882a593Smuzhiyun hex "Preliminary value for OR4" 135*4882a593Smuzhiyun depends on SYS_BR4_PRELIM_BOOL 136*4882a593Smuzhiyun 137*4882a593Smuzhiyunconfig SYS_BR5_PRELIM_BOOL 138*4882a593Smuzhiyun bool "Define Bank 5" 139*4882a593Smuzhiyun 140*4882a593Smuzhiyunconfig SYS_BR5_PRELIM 141*4882a593Smuzhiyun hex "Preliminary value for BR5" 142*4882a593Smuzhiyun depends on SYS_BR5_PRELIM_BOOL 143*4882a593Smuzhiyun 144*4882a593Smuzhiyunconfig SYS_OR5_PRELIM 145*4882a593Smuzhiyun hex "Preliminary value for OR5" 146*4882a593Smuzhiyun depends on SYS_BR5_PRELIM_BOOL 147*4882a593Smuzhiyun 148*4882a593Smuzhiyunconfig SYS_BR6_PRELIM_BOOL 149*4882a593Smuzhiyun bool "Define Bank 6" 150*4882a593Smuzhiyun 151*4882a593Smuzhiyunconfig SYS_BR6_PRELIM 152*4882a593Smuzhiyun hex "Preliminary value for BR6" 153*4882a593Smuzhiyun depends on SYS_BR6_PRELIM_BOOL 154*4882a593Smuzhiyun 155*4882a593Smuzhiyunconfig SYS_OR6_PRELIM 156*4882a593Smuzhiyun hex "Preliminary value for OR6" 157*4882a593Smuzhiyun depends on SYS_BR6_PRELIM_BOOL 158*4882a593Smuzhiyun 159*4882a593Smuzhiyunconfig SYS_BR7_PRELIM_BOOL 160*4882a593Smuzhiyun bool "Define Bank 7" 161*4882a593Smuzhiyun 162*4882a593Smuzhiyunconfig SYS_BR7_PRELIM 163*4882a593Smuzhiyun hex "Preliminary value for BR7" 164*4882a593Smuzhiyun depends on SYS_BR7_PRELIM_BOOL 165*4882a593Smuzhiyun 166*4882a593Smuzhiyunconfig SYS_OR7_PRELIM 167*4882a593Smuzhiyun hex "Preliminary value for OR7" 168*4882a593Smuzhiyun depends on SYS_BR7_PRELIM_BOOL 169*4882a593Smuzhiyun 170*4882a593Smuzhiyunconfig SYS_IMMR 171*4882a593Smuzhiyun hex "Value for IMMR" 172*4882a593Smuzhiyun 173*4882a593Smuzhiyunsource "board/cssi/MCR3000/Kconfig" 174*4882a593Smuzhiyun 175*4882a593Smuzhiyunendmenu 176