1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2010 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <config.h>
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/immap_86xx.h>
11*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define SRDS1_MAX_LANES 4
14*4882a593Smuzhiyun #define SRDS2_MAX_LANES 4
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static u32 serdes1_prtcl_map, serdes2_prtcl_map;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
19*4882a593Smuzhiyun [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1},
20*4882a593Smuzhiyun [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1},
21*4882a593Smuzhiyun [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1},
22*4882a593Smuzhiyun [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1},
23*4882a593Smuzhiyun [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1},
24*4882a593Smuzhiyun [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1},
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
28*4882a593Smuzhiyun [0x3] = {PCIE2, PCIE2, PCIE2, PCIE2},
29*4882a593Smuzhiyun [0x5] = {SRIO1, SRIO1, SRIO1, SRIO1},
30*4882a593Smuzhiyun [0x6] = {SRIO1, SRIO1, SRIO1, SRIO1},
31*4882a593Smuzhiyun [0x7] = {SRIO1, SRIO1, SRIO1, SRIO1},
32*4882a593Smuzhiyun [0x9] = {SRIO1, SRIO1, SRIO1, SRIO1},
33*4882a593Smuzhiyun [0xa] = {SRIO1, SRIO1, SRIO1, SRIO1},
34*4882a593Smuzhiyun [0xb] = {SRIO1, SRIO1, SRIO1, SRIO1},
35*4882a593Smuzhiyun [0xe] = {PCIE2, PCIE2, PCIE2, PCIE2},
36*4882a593Smuzhiyun [0xf] = {PCIE2, PCIE2, PCIE2, PCIE2},
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
is_serdes_configured(enum srds_prtcl device)39*4882a593Smuzhiyun int is_serdes_configured(enum srds_prtcl device)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun int ret;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun if (!(serdes1_prtcl_map & (1 << NONE)))
44*4882a593Smuzhiyun fsl_serdes_init();
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun ret = (1 << device) & serdes1_prtcl_map;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun if (ret)
49*4882a593Smuzhiyun return ret;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun if (!(serdes2_prtcl_map & (1 << NONE)))
52*4882a593Smuzhiyun fsl_serdes_init();
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun return (1 << device) & serdes2_prtcl_map;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
fsl_serdes_init(void)57*4882a593Smuzhiyun void fsl_serdes_init(void)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
60*4882a593Smuzhiyun ccsr_gur_t *gur = &immap->im_gur;
61*4882a593Smuzhiyun u32 pordevsr = in_be32(&gur->pordevsr);
62*4882a593Smuzhiyun u32 srds_cfg = (pordevsr & MPC8641_PORDEVSR_IO_SEL) >>
63*4882a593Smuzhiyun MPC8641_PORDEVSR_IO_SEL_SHIFT;
64*4882a593Smuzhiyun int lane;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun if (serdes1_prtcl_map & (1 << NONE) &&
67*4882a593Smuzhiyun serdes2_prtcl_map & (1 << NONE))
68*4882a593Smuzhiyun return;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
73*4882a593Smuzhiyun printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
74*4882a593Smuzhiyun return;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
77*4882a593Smuzhiyun enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
78*4882a593Smuzhiyun serdes1_prtcl_map |= (1 << lane_prtcl);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* Set the first bit to indicate serdes has been initialized */
82*4882a593Smuzhiyun serdes1_prtcl_map |= (1 << NONE);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) {
85*4882a593Smuzhiyun printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
86*4882a593Smuzhiyun return;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
90*4882a593Smuzhiyun enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
91*4882a593Smuzhiyun serdes2_prtcl_map |= (1 << lane_prtcl);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* Set the first bit to indicate serdes has been initialized */
95*4882a593Smuzhiyun serdes2_prtcl_map |= (1 << NONE);
96*4882a593Smuzhiyun }
97