1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2000-2002
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (C) Copyright 2002 (440 port)
6*4882a593Smuzhiyun * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
9*4882a593Smuzhiyun * Xianghua Xiao (X.Xiao@motorola.com)
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port)
12*4882a593Smuzhiyun * Jeff Brown
13*4882a593Smuzhiyun * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
16*4882a593Smuzhiyun */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <common.h>
19*4882a593Smuzhiyun #include <mpc86xx.h>
20*4882a593Smuzhiyun #include <command.h>
21*4882a593Smuzhiyun #include <asm/processor.h>
22*4882a593Smuzhiyun #ifdef CONFIG_POST
23*4882a593Smuzhiyun #include <post.h>
24*4882a593Smuzhiyun #endif
25*4882a593Smuzhiyun
interrupt_init_cpu(unsigned * decrementer_count)26*4882a593Smuzhiyun void interrupt_init_cpu(unsigned *decrementer_count)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
29*4882a593Smuzhiyun volatile ccsr_pic_t *pic = &immr->im_pic;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #ifdef CONFIG_POST
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun * The POST word is stored in the PIC's TFRR register which gets
34*4882a593Smuzhiyun * cleared when the PIC is reset. Save it off so we can restore it
35*4882a593Smuzhiyun * later.
36*4882a593Smuzhiyun */
37*4882a593Smuzhiyun ulong post_word = post_word_load();
38*4882a593Smuzhiyun #endif
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun pic->gcr = MPC86xx_PICGCR_RST;
41*4882a593Smuzhiyun while (pic->gcr & MPC86xx_PICGCR_RST)
42*4882a593Smuzhiyun ;
43*4882a593Smuzhiyun pic->gcr = MPC86xx_PICGCR_MODE;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
46*4882a593Smuzhiyun debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %d\n",
47*4882a593Smuzhiyun (get_tbclk() / 1000000),
48*4882a593Smuzhiyun *decrementer_count);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #ifdef CONFIG_INTERRUPTS
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */
53*4882a593Smuzhiyun debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
56*4882a593Smuzhiyun debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
59*4882a593Smuzhiyun debug("iivpr3@%p = %x\n", &pic->iivpr3, pic->iivpr3);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
62*4882a593Smuzhiyun pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */
63*4882a593Smuzhiyun debug("iivpr8@%p = %x\n", &pic->iivpr8, pic->iivpr8);
64*4882a593Smuzhiyun #endif
65*4882a593Smuzhiyun #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
66*4882a593Smuzhiyun pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */
67*4882a593Smuzhiyun debug("iivpr9@%p = %x\n", &pic->iivpr9, pic->iivpr9);
68*4882a593Smuzhiyun #endif
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun pic->ctpr = 0; /* 40080 clear current task priority register */
71*4882a593Smuzhiyun #endif
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #ifdef CONFIG_POST
74*4882a593Smuzhiyun post_word_store(post_word);
75*4882a593Smuzhiyun #endif
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /*
79*4882a593Smuzhiyun * timer_interrupt - gets called when the decrementer overflows,
80*4882a593Smuzhiyun * with interrupts disabled.
81*4882a593Smuzhiyun * Trivial implementation - no need to be really accurate.
82*4882a593Smuzhiyun */
timer_interrupt_cpu(struct pt_regs * regs)83*4882a593Smuzhiyun void timer_interrupt_cpu(struct pt_regs *regs)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun /* nothing to do here */
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /*
89*4882a593Smuzhiyun * Install and free a interrupt handler. Not implemented yet.
90*4882a593Smuzhiyun */
irq_install_handler(int vec,interrupt_handler_t * handler,void * arg)91*4882a593Smuzhiyun void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
irq_free_handler(int vec)95*4882a593Smuzhiyun void irq_free_handler(int vec)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /*
100*4882a593Smuzhiyun * irqinfo - print information about PCI devices,not implemented.
101*4882a593Smuzhiyun */
do_irqinfo(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])102*4882a593Smuzhiyun int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun return 0;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /*
108*4882a593Smuzhiyun * Handle external interrupts
109*4882a593Smuzhiyun */
external_interrupt(struct pt_regs * regs)110*4882a593Smuzhiyun void external_interrupt(struct pt_regs *regs)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun puts("external_interrupt (oops!)\n");
113*4882a593Smuzhiyun }
114