1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2004,2009-2011 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun * Jeff Brown
4*4882a593Smuzhiyun * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun /*
10*4882a593Smuzhiyun * cpu_init.c - low level cpu init
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <config.h>
14*4882a593Smuzhiyun #include <common.h>
15*4882a593Smuzhiyun #include <mpc86xx.h>
16*4882a593Smuzhiyun #include <asm/mmu.h>
17*4882a593Smuzhiyun #include <asm/fsl_law.h>
18*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
19*4882a593Smuzhiyun #include <asm/mp.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun extern void srio_init(void);
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /*
26*4882a593Smuzhiyun * Breathe some life into the CPU...
27*4882a593Smuzhiyun *
28*4882a593Smuzhiyun * Set up the memory map
29*4882a593Smuzhiyun * initialize a bunch of registers
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun
cpu_init_f(void)32*4882a593Smuzhiyun void cpu_init_f(void)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun /* Pointer is writable since we allocated a register for it */
35*4882a593Smuzhiyun gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Clear initial global data */
38*4882a593Smuzhiyun memset ((void *) gd, 0, sizeof (gd_t));
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #ifdef CONFIG_FSL_LAW
41*4882a593Smuzhiyun init_laws();
42*4882a593Smuzhiyun #endif
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun setup_bats();
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun init_early_memctl_regs();
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #if defined(CONFIG_FSL_DMA)
49*4882a593Smuzhiyun dma_init();
50*4882a593Smuzhiyun #endif
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* enable the timebase bit in HID0 */
53*4882a593Smuzhiyun set_hid0(get_hid0() | 0x4000000);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* enable EMCP, SYNCBE | ABE bits in HID1 */
56*4882a593Smuzhiyun set_hid1(get_hid1() | 0x80000C00);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /*
60*4882a593Smuzhiyun * initialize higher level parts of CPU like timers
61*4882a593Smuzhiyun */
cpu_init_r(void)62*4882a593Smuzhiyun int cpu_init_r(void)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun /* needs to be in ram since code uses global static vars */
65*4882a593Smuzhiyun fsl_serdes_init();
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #ifdef CONFIG_SYS_SRIO
68*4882a593Smuzhiyun srio_init();
69*4882a593Smuzhiyun #endif
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #if defined(CONFIG_MP)
72*4882a593Smuzhiyun setup_mp();
73*4882a593Smuzhiyun #endif
74*4882a593Smuzhiyun return 0;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #ifdef CONFIG_ADDR_MAP
78*4882a593Smuzhiyun /* Initialize address mapping array */
init_addr_map(void)79*4882a593Smuzhiyun void init_addr_map(void)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun int i;
82*4882a593Smuzhiyun ppc_bat_t bat = DBAT0;
83*4882a593Smuzhiyun phys_size_t size;
84*4882a593Smuzhiyun unsigned long upper, lower;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) {
87*4882a593Smuzhiyun if (read_bat(bat, &upper, &lower) != -1) {
88*4882a593Smuzhiyun if (!BATU_VALID(upper))
89*4882a593Smuzhiyun size = 0;
90*4882a593Smuzhiyun else
91*4882a593Smuzhiyun size = BATU_SIZE(upper);
92*4882a593Smuzhiyun addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
93*4882a593Smuzhiyun size, i);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun #ifdef CONFIG_HIGH_BATS
96*4882a593Smuzhiyun /* High bats are not contiguous with low BAT numbers */
97*4882a593Smuzhiyun if (bat == DBAT3)
98*4882a593Smuzhiyun bat = DBAT4 - 1;
99*4882a593Smuzhiyun #endif
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun #endif
103