1 /*
2 * Copyright 2006,2009-2010 Freescale Semiconductor, Inc.
3 * Jeff Brown
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <common.h>
10 #include <watchdog.h>
11 #include <command.h>
12 #include <asm/cache.h>
13 #include <asm/mmu.h>
14 #include <mpc86xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/ppc.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 /*
21 * Default board reset function
22 */
23 static void
__board_reset(void)24 __board_reset(void)
25 {
26 /* Do nothing */
27 }
28 void board_reset(void) __attribute__((weak, alias("__board_reset")));
29
30
31 int
checkcpu(void)32 checkcpu(void)
33 {
34 sys_info_t sysinfo;
35 uint pvr, svr;
36 uint major, minor;
37 char buf1[32], buf2[32];
38 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
39 volatile ccsr_gur_t *gur = &immap->im_gur;
40 struct cpu_type *cpu;
41 uint msscr0 = mfspr(MSSCR0);
42
43 svr = get_svr();
44 major = SVR_MAJ(svr);
45 minor = SVR_MIN(svr);
46
47 if (cpu_numcores() > 1) {
48 #ifndef CONFIG_MP
49 puts("Unicore software on multiprocessor system!!\n"
50 "To enable mutlticore build define CONFIG_MP\n");
51 #endif
52 }
53 puts("CPU: ");
54
55 cpu = gd->arch.cpu;
56
57 puts(cpu->name);
58
59 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
60 puts("Core: ");
61
62 pvr = get_pvr();
63 major = PVR_E600_MAJ(pvr);
64 minor = PVR_E600_MIN(pvr);
65
66 printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0);
67 if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE)
68 puts("\n Core1Translation Enabled");
69 debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr);
70
71 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
72
73 get_sys_info(&sysinfo);
74
75 puts("Clock Configuration:\n");
76 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor));
77 printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
78 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
79 strmhz(buf1, sysinfo.freq_systembus / 2),
80 strmhz(buf2, sysinfo.freq_systembus));
81
82 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
83 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
84 } else {
85 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
86 sysinfo.freq_localbus);
87 }
88
89 puts("L1: D-cache 32 KiB enabled\n");
90 puts(" I-cache 32 KiB enabled\n");
91
92 puts("L2: ");
93 if (get_l2cr() & 0x80000000) {
94 #if defined(CONFIG_ARCH_MPC8610)
95 puts("256");
96 #elif defined(CONFIG_ARCH_MPC8641)
97 puts("512");
98 #endif
99 puts(" KiB enabled\n");
100 } else {
101 puts("Disabled\n");
102 }
103
104 return 0;
105 }
106
107
do_reset(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])108 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
109 {
110 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
111 volatile ccsr_gur_t *gur = &immap->im_gur;
112
113 /* Attempt board-specific reset */
114 board_reset();
115
116 /* Next try asserting HRESET_REQ */
117 out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ);
118
119 while (1)
120 ;
121
122 return 1;
123 }
124
125
126 /*
127 * Get timebase clock frequency
128 */
129 unsigned long
get_tbclk(void)130 get_tbclk(void)
131 {
132 sys_info_t sys_info;
133
134 get_sys_info(&sys_info);
135 return (sys_info.freq_systembus + 3L) / 4L;
136 }
137
138
139 #if defined(CONFIG_WATCHDOG)
140 void
watchdog_reset(void)141 watchdog_reset(void)
142 {
143 #if defined(CONFIG_ARCH_MPC8610)
144 /*
145 * This actually feed the hard enabled watchdog.
146 */
147 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
148 volatile ccsr_wdt_t *wdt = &immap->im_wdt;
149 volatile ccsr_gur_t *gur = &immap->im_gur;
150 u32 tmp = gur->pordevsr;
151
152 if (tmp & 0x4000) {
153 wdt->swsrr = 0x556c;
154 wdt->swsrr = 0xaa39;
155 }
156 #endif
157 }
158 #endif /* CONFIG_WATCHDOG */
159
160 /*
161 * Print out the state of various machine registers.
162 * Currently prints out LAWs, BR0/OR0, and BATs
163 */
print_reginfo(void)164 void print_reginfo(void)
165 {
166 print_bats();
167 print_laws();
168 print_lbc_regs();
169 }
170
171 /*
172 * Set the DDR BATs to reflect the actual size of DDR.
173 *
174 * dram_size is the actual size of DDR, in bytes
175 *
176 * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only
177 * are using a single BAT to cover DDR.
178 *
179 * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN
180 * is not defined) then we might have a situation where U-Boot will attempt
181 * to relocated itself outside of the region mapped by DBAT0.
182 * This will cause a machine check.
183 *
184 * Currently we are limited to power of two sized DDR since we only use a
185 * single bat. If a non-power of two size is used that is less than
186 * CONFIG_MAX_MEM_MAPPED u-boot will crash.
187 *
188 */
setup_ddr_bat(phys_addr_t dram_size)189 void setup_ddr_bat(phys_addr_t dram_size)
190 {
191 unsigned long batu, bl;
192
193 bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED));
194
195 if (BATU_SIZE(bl) != dram_size) {
196 u64 sz = (u64)dram_size - BATU_SIZE(bl);
197 print_size(sz, " left unmapped\n");
198 }
199
200 batu = bl | BATU_VS | BATU_VP;
201 write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L);
202 write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L);
203 }
204