1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright 2007-2009, 2011 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "config.h" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#ifdef CONFIG_RESET_VECTOR_ADDRESS 10*4882a593Smuzhiyun#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS 11*4882a593Smuzhiyun#else 12*4882a593Smuzhiyun#define RESET_VECTOR_ADDRESS 0xfffffffc 13*4882a593Smuzhiyun#endif 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun#ifndef CONFIG_SYS_MONITOR_LEN 16*4882a593Smuzhiyun#define CONFIG_SYS_MONITOR_LEN 0x80000 17*4882a593Smuzhiyun#endif 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunOUTPUT_ARCH(powerpc) 20*4882a593SmuzhiyunENTRY(_start_e500) 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunPHDRS 23*4882a593Smuzhiyun{ 24*4882a593Smuzhiyun text PT_LOAD; 25*4882a593Smuzhiyun bss PT_LOAD; 26*4882a593Smuzhiyun} 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunSECTIONS 29*4882a593Smuzhiyun{ 30*4882a593Smuzhiyun /* Read-only sections, merged into text segment: */ 31*4882a593Smuzhiyun . = + SIZEOF_HEADERS; 32*4882a593Smuzhiyun .interp : { *(.interp) } 33*4882a593Smuzhiyun .text : 34*4882a593Smuzhiyun { 35*4882a593Smuzhiyun *(.text*) 36*4882a593Smuzhiyun } :text 37*4882a593Smuzhiyun _etext = .; 38*4882a593Smuzhiyun PROVIDE (etext = .); 39*4882a593Smuzhiyun .rodata : 40*4882a593Smuzhiyun { 41*4882a593Smuzhiyun *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) 42*4882a593Smuzhiyun } :text 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Read-write section, merged into data segment: */ 45*4882a593Smuzhiyun . = (. + 0x00FF) & 0xFFFFFF00; 46*4882a593Smuzhiyun _erotext = .; 47*4882a593Smuzhiyun PROVIDE (erotext = .); 48*4882a593Smuzhiyun .reloc : 49*4882a593Smuzhiyun { 50*4882a593Smuzhiyun _GOT2_TABLE_ = .; 51*4882a593Smuzhiyun KEEP(*(.got2)) 52*4882a593Smuzhiyun KEEP(*(.got)) 53*4882a593Smuzhiyun _FIXUP_TABLE_ = .; 54*4882a593Smuzhiyun KEEP(*(.fixup)) 55*4882a593Smuzhiyun } 56*4882a593Smuzhiyun __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; 57*4882a593Smuzhiyun __fixup_entries = (. - _FIXUP_TABLE_) >> 2; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun .data : 60*4882a593Smuzhiyun { 61*4882a593Smuzhiyun *(.data*) 62*4882a593Smuzhiyun *(.sdata*) 63*4882a593Smuzhiyun } 64*4882a593Smuzhiyun _edata = .; 65*4882a593Smuzhiyun PROVIDE (edata = .); 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun . = .; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun . = ALIGN(4); 70*4882a593Smuzhiyun .u_boot_list : { 71*4882a593Smuzhiyun KEEP(*(SORT(.u_boot_list*))); 72*4882a593Smuzhiyun } 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun . = .; 75*4882a593Smuzhiyun __start___ex_table = .; 76*4882a593Smuzhiyun __ex_table : { *(__ex_table) } 77*4882a593Smuzhiyun __stop___ex_table = .; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun . = ALIGN(256); 80*4882a593Smuzhiyun __init_begin = .; 81*4882a593Smuzhiyun .text.init : { *(.text.init) } 82*4882a593Smuzhiyun .data.init : { *(.data.init) } 83*4882a593Smuzhiyun . = ALIGN(256); 84*4882a593Smuzhiyun __init_end = .; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC 87*4882a593Smuzhiyun .bootpg ADDR(.text) - 0x1000 : 88*4882a593Smuzhiyun { 89*4882a593Smuzhiyun KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) 90*4882a593Smuzhiyun } :text = 0xffff 91*4882a593Smuzhiyun . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN; 92*4882a593Smuzhiyun#else 93*4882a593Smuzhiyun .bootpg RESET_VECTOR_ADDRESS - 0xffc : 94*4882a593Smuzhiyun { 95*4882a593Smuzhiyun arch/powerpc/cpu/mpc85xx/start.o (.bootpg) 96*4882a593Smuzhiyun } :text = 0xffff 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun .resetvec RESET_VECTOR_ADDRESS : 99*4882a593Smuzhiyun { 100*4882a593Smuzhiyun KEEP(*(.resetvec)) 101*4882a593Smuzhiyun } :text = 0xffff 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun . = RESET_VECTOR_ADDRESS + 0x4; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* 106*4882a593Smuzhiyun * Make sure that the bss segment isn't linked at 0x0, otherwise its 107*4882a593Smuzhiyun * address won't be updated during relocation fixups. Note that 108*4882a593Smuzhiyun * this is a temporary fix. Code to dynamically the fixup the bss 109*4882a593Smuzhiyun * location will be added in the future. When the bss relocation 110*4882a593Smuzhiyun * fixup code is present this workaround should be removed. 111*4882a593Smuzhiyun */ 112*4882a593Smuzhiyun#if (RESET_VECTOR_ADDRESS == 0xfffffffc) 113*4882a593Smuzhiyun . |= 0x10; 114*4882a593Smuzhiyun#endif 115*4882a593Smuzhiyun#endif 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun __bss_start = .; 118*4882a593Smuzhiyun .bss (NOLOAD) : 119*4882a593Smuzhiyun { 120*4882a593Smuzhiyun *(.sbss*) 121*4882a593Smuzhiyun *(.bss*) 122*4882a593Smuzhiyun *(COMMON) 123*4882a593Smuzhiyun } :bss 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun . = ALIGN(4); 126*4882a593Smuzhiyun __bss_end = . ; 127*4882a593Smuzhiyun PROVIDE (end = .); 128*4882a593Smuzhiyun} 129