1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2012 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
9*4882a593Smuzhiyun #include <asm/processor.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
14*4882a593Smuzhiyun [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
15*4882a593Smuzhiyun PCIE2, PCIE2, PCIE2, PCIE2},
16*4882a593Smuzhiyun [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
17*4882a593Smuzhiyun PCIE2, PCIE3, PCIE4, SATA1},
18*4882a593Smuzhiyun [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
19*4882a593Smuzhiyun PCIE2, PCIE3, SATA2, SATA1},
20*4882a593Smuzhiyun [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
21*4882a593Smuzhiyun PCIE2, PCIE2, PCIE2, PCIE2},
22*4882a593Smuzhiyun [0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
23*4882a593Smuzhiyun PCIE2, PCIE2, PCIE2, PCIE2},
24*4882a593Smuzhiyun [0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
25*4882a593Smuzhiyun PCIE2, PCIE3, PCIE4, SATA1},
26*4882a593Smuzhiyun [0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
27*4882a593Smuzhiyun PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
28*4882a593Smuzhiyun [0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
29*4882a593Smuzhiyun PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
30*4882a593Smuzhiyun [0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
31*4882a593Smuzhiyun PCIE2, PCIE3, PCIE4, SATA1},
32*4882a593Smuzhiyun [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
33*4882a593Smuzhiyun PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
34*4882a593Smuzhiyun [0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
35*4882a593Smuzhiyun PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
36*4882a593Smuzhiyun [0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
37*4882a593Smuzhiyun PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},
38*4882a593Smuzhiyun [0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
39*4882a593Smuzhiyun PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5},
40*4882a593Smuzhiyun [0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
41*4882a593Smuzhiyun AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
42*4882a593Smuzhiyun [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
43*4882a593Smuzhiyun PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
44*4882a593Smuzhiyun [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
45*4882a593Smuzhiyun PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
46*4882a593Smuzhiyun [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
47*4882a593Smuzhiyun PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
serdes_get_prtcl(int serdes,int cfg,int lane)50*4882a593Smuzhiyun enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun return serdes_cfg_tbl[cfg][lane];
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
is_serdes_prtcl_valid(int serdes,u32 prtcl)55*4882a593Smuzhiyun int is_serdes_prtcl_valid(int serdes, u32 prtcl)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun int i;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
60*4882a593Smuzhiyun return 0;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun for (i = 0; i < SRDS_MAX_LANES; i++) {
63*4882a593Smuzhiyun if (serdes_cfg_tbl[prtcl][i] != NONE)
64*4882a593Smuzhiyun return 1;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return 0;
68*4882a593Smuzhiyun }
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