1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
9*4882a593Smuzhiyun #include <asm/processor.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
14*4882a593Smuzhiyun [0x40] = {PCIE1, PCIE1, PCIE1, PCIE1},
15*4882a593Smuzhiyun [0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
16*4882a593Smuzhiyun [0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1},
17*4882a593Smuzhiyun [0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1},
18*4882a593Smuzhiyun [0x99] = {XFI_FM1_MAC1, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
19*4882a593Smuzhiyun [0x46] = {PCIE1, PCIE1, PCIE2, SATA1},
20*4882a593Smuzhiyun [0x47] = {PCIE1, PCIE1, PCIE2, SGMII_FM1_DTSEC1},
21*4882a593Smuzhiyun [0x56] = {PCIE1, PCIE3, PCIE2, SATA1},
22*4882a593Smuzhiyun [0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1},
23*4882a593Smuzhiyun [0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
24*4882a593Smuzhiyun [0x5F] = {PCIE1, PCIE3, SGMII_2500_FM1_DTSEC2, SGMII_2500_FM1_DTSEC1},
25*4882a593Smuzhiyun [0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1},
26*4882a593Smuzhiyun [0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
27*4882a593Smuzhiyun [0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
28*4882a593Smuzhiyun SGMII_2500_FM1_DTSEC1},
29*4882a593Smuzhiyun [0x77] = {PCIE1, SGMII_2500_FM1_DTSEC3, PCIE2, SGMII_FM1_DTSEC1},
30*4882a593Smuzhiyun [0x7F] = {PCIE1, SGMII_2500_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
31*4882a593Smuzhiyun SGMII_2500_FM1_DTSEC1},
32*4882a593Smuzhiyun [0x119] = {AURORA, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
33*4882a593Smuzhiyun [0x135] = {AURORA, SGMII_2500_FM1_DTSEC3, PCIE2, PCIE1},
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun
serdes_get_prtcl(int serdes,int cfg,int lane)36*4882a593Smuzhiyun enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun return serdes_cfg_tbl[cfg][lane];
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
is_serdes_prtcl_valid(int serdes,u32 prtcl)41*4882a593Smuzhiyun int is_serdes_prtcl_valid(int serdes, u32 prtcl)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun int i;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
46*4882a593Smuzhiyun return 0;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun for (i = 0; i < SRDS_MAX_LANES; i++) {
49*4882a593Smuzhiyun if (serdes_cfg_tbl[prtcl][i] != NONE)
50*4882a593Smuzhiyun return 1;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun return 0;
54*4882a593Smuzhiyun }
55