1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2009 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/processor.h> 9*4882a593Smuzhiyun #include <asm/global_data.h> 10*4882a593Smuzhiyun #include <fsl_ifc.h> 11*4882a593Smuzhiyun #include <asm/io.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 14*4882a593Smuzhiyun cpu_init_f(void)15*4882a593Smuzhiyunulong cpu_init_f(void) 16*4882a593Smuzhiyun { 17*4882a593Smuzhiyun #ifdef CONFIG_SYS_INIT_L2_ADDR 18*4882a593Smuzhiyun ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* set MBECCDIS=1, SBECCDIS=1 */ 23*4882a593Smuzhiyun out_be32(&l2cache->l2errdis, 24*4882a593Smuzhiyun (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* set L2E=1 & L2SRAM=001 */ 27*4882a593Smuzhiyun out_be32(&l2cache->l2ctl, 28*4882a593Smuzhiyun (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun return 0; 32*4882a593Smuzhiyun } 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #ifndef CONFIG_SYS_FSL_TBCLK_DIV 35*4882a593Smuzhiyun #define CONFIG_SYS_FSL_TBCLK_DIV 8 36*4882a593Smuzhiyun #endif 37*4882a593Smuzhiyun udelay(unsigned long usec)38*4882a593Smuzhiyunvoid udelay(unsigned long usec) 39*4882a593Smuzhiyun { 40*4882a593Smuzhiyun u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000); 41*4882a593Smuzhiyun u32 ticks = ticks_per_usec * usec; 42*4882a593Smuzhiyun u32 s = mfspr(SPRN_TBRL); 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun while ((mfspr(SPRN_TBRL) - s) < ticks); 45*4882a593Smuzhiyun } 46