1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2006 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Dave Liu <daveliu@freescale.com>
5*4882a593Smuzhiyun * based on source code of Shlomi Gridish
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <linux/errno.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <asm/immap_85xx.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
16*4882a593Smuzhiyun #define NUM_OF_PINS 32
qe_config_iopin(u8 port,u8 pin,int dir,int open_drain,int assign)17*4882a593Smuzhiyun void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun u32 pin_2bit_mask;
20*4882a593Smuzhiyun u32 pin_2bit_dir;
21*4882a593Smuzhiyun u32 pin_2bit_assign;
22*4882a593Smuzhiyun u32 pin_1bit_mask;
23*4882a593Smuzhiyun u32 tmp_val;
24*4882a593Smuzhiyun volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
25*4882a593Smuzhiyun volatile par_io_t *par_io = (volatile par_io_t *)
26*4882a593Smuzhiyun &(gur->qe_par_io);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* Caculate pin location and 2bit mask and dir */
29*4882a593Smuzhiyun pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
30*4882a593Smuzhiyun pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* Setup the direction */
33*4882a593Smuzhiyun tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \
34*4882a593Smuzhiyun in_be32(&par_io[port].cpdir2) :
35*4882a593Smuzhiyun in_be32(&par_io[port].cpdir1);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun if (pin > (NUM_OF_PINS/2) -1) {
38*4882a593Smuzhiyun out_be32(&par_io[port].cpdir2, ~pin_2bit_mask & tmp_val);
39*4882a593Smuzhiyun out_be32(&par_io[port].cpdir2, pin_2bit_dir | tmp_val);
40*4882a593Smuzhiyun } else {
41*4882a593Smuzhiyun out_be32(&par_io[port].cpdir1, ~pin_2bit_mask & tmp_val);
42*4882a593Smuzhiyun out_be32(&par_io[port].cpdir1, pin_2bit_dir | tmp_val);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* Calculate pin location for 1bit mask */
46*4882a593Smuzhiyun pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1)));
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* Setup the open drain */
49*4882a593Smuzhiyun tmp_val = in_be32(&par_io[port].cpodr);
50*4882a593Smuzhiyun if (open_drain)
51*4882a593Smuzhiyun out_be32(&par_io[port].cpodr, pin_1bit_mask | tmp_val);
52*4882a593Smuzhiyun else
53*4882a593Smuzhiyun out_be32(&par_io[port].cpodr, ~pin_1bit_mask & tmp_val);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* Setup the assignment */
56*4882a593Smuzhiyun tmp_val = (pin > (NUM_OF_PINS/2) - 1) ?
57*4882a593Smuzhiyun in_be32(&par_io[port].cppar2):
58*4882a593Smuzhiyun in_be32(&par_io[port].cppar1);
59*4882a593Smuzhiyun pin_2bit_assign = (u32)(assign
60*4882a593Smuzhiyun << (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2));
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* Clear and set 2 bits mask */
63*4882a593Smuzhiyun if (pin > (NUM_OF_PINS/2) - 1) {
64*4882a593Smuzhiyun out_be32(&par_io[port].cppar2, ~pin_2bit_mask & tmp_val);
65*4882a593Smuzhiyun out_be32(&par_io[port].cppar2, pin_2bit_assign | tmp_val);
66*4882a593Smuzhiyun } else {
67*4882a593Smuzhiyun out_be32(&par_io[port].cppar1, ~pin_2bit_mask & tmp_val);
68*4882a593Smuzhiyun out_be32(&par_io[port].cppar1, pin_2bit_assign | tmp_val);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #endif /* CONFIG_QE */
73