1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2009-2011 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
9*4882a593Smuzhiyun #include <asm/processor.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include "fsl_corenet_serdes.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun * Note: For P5040, the fourth SerDes bank (with two lanes) is on SerDes2, but
15*4882a593Smuzhiyun * U-Boot only supports one SerDes controller. Therefore, we ignore bank 4 in
16*4882a593Smuzhiyun * this table. This works because most of the SerDes code is for errata
17*4882a593Smuzhiyun * work-arounds, and there are no P5040 errata that effect bank 4.
18*4882a593Smuzhiyun */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
21*4882a593Smuzhiyun [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
22*4882a593Smuzhiyun SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
23*4882a593Smuzhiyun SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
24*4882a593Smuzhiyun XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2, */ },
25*4882a593Smuzhiyun [0x01] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
26*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
27*4882a593Smuzhiyun XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
28*4882a593Smuzhiyun XAUI_FM2, /* SATA1, SATA2 */ },
29*4882a593Smuzhiyun [0x02] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
30*4882a593Smuzhiyun SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
31*4882a593Smuzhiyun XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
32*4882a593Smuzhiyun XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
33*4882a593Smuzhiyun [0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC1,
34*4882a593Smuzhiyun SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
35*4882a593Smuzhiyun SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
36*4882a593Smuzhiyun SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
37*4882a593Smuzhiyun /* SATA1, SATA2 */ },
38*4882a593Smuzhiyun [0x04] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM2_DTSEC1,
39*4882a593Smuzhiyun SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
40*4882a593Smuzhiyun SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
41*4882a593Smuzhiyun SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
42*4882a593Smuzhiyun /* SATA1, SATA2 */ },
43*4882a593Smuzhiyun [0x05] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC3,
44*4882a593Smuzhiyun SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
45*4882a593Smuzhiyun XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
46*4882a593Smuzhiyun XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
47*4882a593Smuzhiyun [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
48*4882a593Smuzhiyun SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
49*4882a593Smuzhiyun SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
50*4882a593Smuzhiyun XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
51*4882a593Smuzhiyun [0x07] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
52*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
53*4882a593Smuzhiyun XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
54*4882a593Smuzhiyun XAUI_FM2, /* SATA1, SATA2 */ },
55*4882a593Smuzhiyun [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
56*4882a593Smuzhiyun AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
57*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2,
58*4882a593Smuzhiyun /* NONE, NONE */ },
59*4882a593Smuzhiyun [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
60*4882a593Smuzhiyun AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
61*4882a593Smuzhiyun NONE, NONE, SATA1, SATA2, /* NONE, NONE */ },
62*4882a593Smuzhiyun [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
63*4882a593Smuzhiyun AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
64*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2,
65*4882a593Smuzhiyun XAUI_FM2, XAUI_FM2, /* NONE, NONE */ },
66*4882a593Smuzhiyun [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
67*4882a593Smuzhiyun SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
68*4882a593Smuzhiyun AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
69*4882a593Smuzhiyun NONE, SATA1, SATA2, /* NONE, NONE */ },
70*4882a593Smuzhiyun [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
71*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
72*4882a593Smuzhiyun XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2,
73*4882a593Smuzhiyun /* NONE, NONE */ },
74*4882a593Smuzhiyun [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
75*4882a593Smuzhiyun SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
76*4882a593Smuzhiyun AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
77*4882a593Smuzhiyun NONE, SATA1, SATA2, /* NONE, NONE */ },
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun
serdes_get_prtcl(int cfg,int lane)80*4882a593Smuzhiyun enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun if (!serdes_lane_enabled(lane))
83*4882a593Smuzhiyun return NONE;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return serdes_cfg_tbl[cfg][lane];
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
is_serdes_prtcl_valid(u32 prtcl)88*4882a593Smuzhiyun int is_serdes_prtcl_valid(u32 prtcl)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun int i;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
93*4882a593Smuzhiyun return 0;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun for (i = 0; i < SRDS_MAX_LANES; i++) {
96*4882a593Smuzhiyun if (serdes_cfg_tbl[prtcl][i] != NONE)
97*4882a593Smuzhiyun return 1;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return 0;
101*4882a593Smuzhiyun }
102