1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2009-2010 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
10*4882a593Smuzhiyun #include <asm/processor.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include "fsl_corenet_serdes.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
15*4882a593Smuzhiyun [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
16*4882a593Smuzhiyun AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
17*4882a593Smuzhiyun XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
18*4882a593Smuzhiyun [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
19*4882a593Smuzhiyun AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
20*4882a593Smuzhiyun XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
21*4882a593Smuzhiyun [0x8] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
22*4882a593Smuzhiyun AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
23*4882a593Smuzhiyun XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
24*4882a593Smuzhiyun [0xd] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
25*4882a593Smuzhiyun SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
26*4882a593Smuzhiyun XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
27*4882a593Smuzhiyun [0xe] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
28*4882a593Smuzhiyun SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
29*4882a593Smuzhiyun XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
30*4882a593Smuzhiyun [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
31*4882a593Smuzhiyun SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2,
32*4882a593Smuzhiyun XAUI_FM2, XAUI_FM2, XAUI_FM2, NONE, NONE, NONE, NONE},
33*4882a593Smuzhiyun [0x10] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM2_DTSEC1,
34*4882a593Smuzhiyun SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
35*4882a593Smuzhiyun AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
36*4882a593Smuzhiyun NONE, NONE, NONE, NONE},
37*4882a593Smuzhiyun [0x13] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
38*4882a593Smuzhiyun AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
39*4882a593Smuzhiyun XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
40*4882a593Smuzhiyun [0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
41*4882a593Smuzhiyun AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
42*4882a593Smuzhiyun SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
43*4882a593Smuzhiyun SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
44*4882a593Smuzhiyun [0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
45*4882a593Smuzhiyun AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
46*4882a593Smuzhiyun SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
47*4882a593Smuzhiyun [0x1d] = {PCIE1, PCIE1, PCIE3, PCIE3, NONE, SRIO2, NONE, SRIO1,
48*4882a593Smuzhiyun AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
49*4882a593Smuzhiyun XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
50*4882a593Smuzhiyun [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
51*4882a593Smuzhiyun AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
52*4882a593Smuzhiyun XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
53*4882a593Smuzhiyun [0x25] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
54*4882a593Smuzhiyun AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
55*4882a593Smuzhiyun XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
59*4882a593Smuzhiyun uint16_t srds_lpd_b[SRDS_MAX_BANK];
60*4882a593Smuzhiyun #endif
61*4882a593Smuzhiyun
serdes_get_prtcl(int cfg,int lane)62*4882a593Smuzhiyun enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun if (!serdes_lane_enabled(lane))
65*4882a593Smuzhiyun return NONE;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun return serdes_cfg_tbl[cfg][lane];
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
is_serdes_prtcl_valid(u32 prtcl)70*4882a593Smuzhiyun int is_serdes_prtcl_valid(u32 prtcl) {
71*4882a593Smuzhiyun int i;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
74*4882a593Smuzhiyun return 0;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun for (i = 0; i < SRDS_MAX_LANES; i++) {
77*4882a593Smuzhiyun if (serdes_cfg_tbl[prtcl][i] != NONE)
78*4882a593Smuzhiyun return 1;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return 0;
82*4882a593Smuzhiyun }
83