1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2010-2011 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
9*4882a593Smuzhiyun #include <asm/processor.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include "fsl_corenet_serdes.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
14*4882a593Smuzhiyun [0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
15*4882a593Smuzhiyun NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
16*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
17*4882a593Smuzhiyun [0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
18*4882a593Smuzhiyun NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
19*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
20*4882a593Smuzhiyun [0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
21*4882a593Smuzhiyun PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1,
22*4882a593Smuzhiyun SATA2, NONE, NONE, NONE, NONE, },
23*4882a593Smuzhiyun [0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
24*4882a593Smuzhiyun PCIE2, PCIE2, PCIE2, NONE, NONE, XAUI_FM1, XAUI_FM1,
25*4882a593Smuzhiyun XAUI_FM1, XAUI_FM1, NONE, NONE, NONE, NONE, },
26*4882a593Smuzhiyun [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
27*4882a593Smuzhiyun PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3,
28*4882a593Smuzhiyun PCIE3, NONE, NONE, NONE, NONE, },
29*4882a593Smuzhiyun [0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
30*4882a593Smuzhiyun SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5,
31*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
32*4882a593Smuzhiyun [0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
33*4882a593Smuzhiyun PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA,
34*4882a593Smuzhiyun SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE,
35*4882a593Smuzhiyun NONE, NONE, NONE, },
36*4882a593Smuzhiyun [0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
37*4882a593Smuzhiyun SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE,
38*4882a593Smuzhiyun NONE, NONE, NONE, },
39*4882a593Smuzhiyun [0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
40*4882a593Smuzhiyun SGMII_FM1_DTSEC4, NONE, NONE, XAUI_FM1, XAUI_FM1, XAUI_FM1,
41*4882a593Smuzhiyun XAUI_FM1, NONE, NONE, NONE, NONE, },
42*4882a593Smuzhiyun [0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
43*4882a593Smuzhiyun PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
44*4882a593Smuzhiyun NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
45*4882a593Smuzhiyun [0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
46*4882a593Smuzhiyun SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
47*4882a593Smuzhiyun NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
48*4882a593Smuzhiyun [0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2,
49*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA,
50*4882a593Smuzhiyun SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, },
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
serdes_get_prtcl(int cfg,int lane)53*4882a593Smuzhiyun enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun enum srds_prtcl prtcl;
56*4882a593Smuzhiyun u32 svr = get_svr();
57*4882a593Smuzhiyun u32 ver = SVR_SOC_VER(svr);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun if (!serdes_lane_enabled(lane))
60*4882a593Smuzhiyun return NONE;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun prtcl = serdes_cfg_tbl[cfg][lane];
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* P2040[e] does not support XAUI */
65*4882a593Smuzhiyun if (ver == SVR_P2040 && prtcl == XAUI_FM1)
66*4882a593Smuzhiyun prtcl = NONE;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return prtcl;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
is_serdes_prtcl_valid(u32 prtcl)71*4882a593Smuzhiyun int is_serdes_prtcl_valid(u32 prtcl)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun int i;
74*4882a593Smuzhiyun u32 svr = get_svr();
75*4882a593Smuzhiyun u32 ver = SVR_SOC_VER(svr);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
78*4882a593Smuzhiyun return 0;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* P2040[e] does not support XAUI */
81*4882a593Smuzhiyun if (ver == SVR_P2040 && prtcl == XAUI_FM1)
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun for (i = 0; i < SRDS_MAX_LANES; i++) {
85*4882a593Smuzhiyun if (serdes_cfg_tbl[prtcl][i] != NONE)
86*4882a593Smuzhiyun return 1;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun return 0;
90*4882a593Smuzhiyun }
91