1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2010 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <config.h>
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/immap_85xx.h>
11*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define SRDS1_MAX_LANES 4
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static u32 serdes1_prtcl_map;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
18*4882a593Smuzhiyun [0x0] = {PCIE1, NONE, NONE, NONE},
19*4882a593Smuzhiyun [0x1] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2},
20*4882a593Smuzhiyun [0x2] = {SRIO1, SRIO2, SGMII_TSEC1, SGMII_TSEC2},
21*4882a593Smuzhiyun [0x3] = {SRIO1, SRIO2, NONE, NONE},
22*4882a593Smuzhiyun [0x4] = {PCIE1, NONE, SGMII_TSEC1, SGMII_TSEC2},
23*4882a593Smuzhiyun [0x5] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
24*4882a593Smuzhiyun [0x6] = {PCIE1, NONE, SRIO1, SRIO2},
25*4882a593Smuzhiyun [0x7] = {PCIE1, PCIE1, SRIO1, SRIO2},
26*4882a593Smuzhiyun [0x8] = {PCIE1, PCIE1, SRIO1, SRIO2},
27*4882a593Smuzhiyun [0x9] = {SRIO1, SRIO1, SRIO1, SRIO1},
28*4882a593Smuzhiyun [0xa] = {SRIO1, SRIO1, SRIO1, SRIO1},
29*4882a593Smuzhiyun [0xb] = {SRIO1, SRIO1, SRIO1, SRIO1},
30*4882a593Smuzhiyun [0xc] = {PCIE1, SRIO1, SGMII_TSEC1, SGMII_TSEC2},
31*4882a593Smuzhiyun [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1},
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
is_serdes_configured(enum srds_prtcl prtcl)34*4882a593Smuzhiyun int is_serdes_configured(enum srds_prtcl prtcl)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun if (!(serdes1_prtcl_map & (1 << NONE)))
37*4882a593Smuzhiyun fsl_serdes_init();
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun return (1 << prtcl) & serdes1_prtcl_map;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
fsl_serdes_init(void)42*4882a593Smuzhiyun void fsl_serdes_init(void)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
45*4882a593Smuzhiyun u32 pordevsr = in_be32(&gur->pordevsr);
46*4882a593Smuzhiyun u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
47*4882a593Smuzhiyun MPC85xx_PORDEVSR_IO_SEL_SHIFT;
48*4882a593Smuzhiyun int lane;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun if (serdes1_prtcl_map & (1 << NONE))
51*4882a593Smuzhiyun return;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
56*4882a593Smuzhiyun printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
57*4882a593Smuzhiyun return;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
61*4882a593Smuzhiyun enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
62*4882a593Smuzhiyun serdes1_prtcl_map |= (1 << lane_prtcl);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Set the first bit to indicate serdes has been initialized */
66*4882a593Smuzhiyun serdes1_prtcl_map |= (1 << NONE);
67*4882a593Smuzhiyun }
68