1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2000-2002
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * (C) Copyright 2002 (440 port)
6*4882a593Smuzhiyun * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
9*4882a593Smuzhiyun * Xianghua Xiao (X.Xiao@motorola.com)
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <common.h>
15*4882a593Smuzhiyun #include <watchdog.h>
16*4882a593Smuzhiyun #include <command.h>
17*4882a593Smuzhiyun #include <asm/processor.h>
18*4882a593Smuzhiyun #include <asm/io.h>
19*4882a593Smuzhiyun #ifdef CONFIG_POST
20*4882a593Smuzhiyun #include <post.h>
21*4882a593Smuzhiyun #endif
22*4882a593Smuzhiyun
interrupt_init_cpu(unsigned * decrementer_count)23*4882a593Smuzhiyun void interrupt_init_cpu(unsigned *decrementer_count)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #ifdef CONFIG_POST
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun * The POST word is stored in the PIC's TFRR register which gets
30*4882a593Smuzhiyun * cleared when the PIC is reset. Save it off so we can restore it
31*4882a593Smuzhiyun * later.
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun ulong post_word = post_word_load();
34*4882a593Smuzhiyun #endif
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
37*4882a593Smuzhiyun while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)
38*4882a593Smuzhiyun ;
39*4882a593Smuzhiyun out_be32(&pic->gcr, MPC85xx_PICGCR_M);
40*4882a593Smuzhiyun in_be32(&pic->gcr);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* PIE is same as DIE, dec interrupt enable */
45*4882a593Smuzhiyun mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #ifdef CONFIG_INTERRUPTS
48*4882a593Smuzhiyun pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */
49*4882a593Smuzhiyun debug("iivpr1@%x = %x\n", (uint)&pic->iivpr1, pic->iivpr1);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
52*4882a593Smuzhiyun debug("iivpr2@%x = %x\n", (uint)&pic->iivpr2, pic->iivpr2);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
55*4882a593Smuzhiyun debug("iivpr3@%x = %x\n", (uint)&pic->iivpr3, pic->iivpr3);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #ifdef CONFIG_PCI1
58*4882a593Smuzhiyun pic->iivpr8 = 0x810008; /* enable pci1 interrupts */
59*4882a593Smuzhiyun debug("iivpr8@%x = %x\n", (uint)&pic->iivpr8, pic->iivpr8);
60*4882a593Smuzhiyun #endif
61*4882a593Smuzhiyun #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
62*4882a593Smuzhiyun pic->iivpr9 = 0x810009; /* enable pci1 interrupts */
63*4882a593Smuzhiyun debug("iivpr9@%x = %x\n", (uint)&pic->iivpr9, pic->iivpr9);
64*4882a593Smuzhiyun #endif
65*4882a593Smuzhiyun #ifdef CONFIG_PCIE1
66*4882a593Smuzhiyun pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */
67*4882a593Smuzhiyun debug("iivpr10@%x = %x\n", (uint)&pic->iivpr10, pic->iivpr10);
68*4882a593Smuzhiyun #endif
69*4882a593Smuzhiyun #ifdef CONFIG_PCIE3
70*4882a593Smuzhiyun pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */
71*4882a593Smuzhiyun debug("iivpr11@%x = %x\n", (uint)&pic->iivpr11, pic->iivpr11);
72*4882a593Smuzhiyun #endif
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun pic->ctpr=0; /* 40080 clear current task priority register */
75*4882a593Smuzhiyun #endif
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #ifdef CONFIG_POST
78*4882a593Smuzhiyun post_word_store(post_word);
79*4882a593Smuzhiyun #endif
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Install and free a interrupt handler. Not implemented yet. */
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun void
irq_install_handler(int vec,interrupt_handler_t * handler,void * arg)85*4882a593Smuzhiyun irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun return;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun void
irq_free_handler(int vec)91*4882a593Smuzhiyun irq_free_handler(int vec)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun return;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
timer_interrupt_cpu(struct pt_regs * regs)96*4882a593Smuzhiyun void timer_interrupt_cpu(struct pt_regs *regs)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun /* PIS is same as DIS, dec interrupt status */
99*4882a593Smuzhiyun mtspr(SPRN_TSR, TSR_PIS);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #if defined(CONFIG_CMD_IRQ)
103*4882a593Smuzhiyun /* irqinfo - print information about PCI devices,not implemented. */
do_irqinfo(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])104*4882a593Smuzhiyun int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun return 0;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun #endif
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