1 /*
2 * Copyright 2009-2012 Freescale Semiconductor, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <asm/processor.h>
9 #include <asm/mmu.h>
10 #include <asm/fsl_law.h>
11 #include <asm/io.h>
12
13 DECLARE_GLOBAL_DATA_PTR;
14
15 #ifdef CONFIG_A003399_NOR_WORKAROUND
setup_ifc(void)16 void setup_ifc(void)
17 {
18 struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
19 u32 _mas0, _mas1, _mas2, _mas3, _mas7;
20 phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
21
22 /*
23 * Adjust the TLB we were running out of to match the phys addr of the
24 * chip select we are adjusting and will return to.
25 */
26 flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
27
28 _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
29 _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
30 MAS1_TSIZE(BOOKE_PAGESZ_4M);
31 _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
32 _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
33 _mas7 = FSL_BOOKE_MAS7(flash_phys);
34
35 mtspr(MAS0, _mas0);
36 mtspr(MAS1, _mas1);
37 mtspr(MAS2, _mas2);
38 mtspr(MAS3, _mas3);
39 mtspr(MAS7, _mas7);
40
41 asm volatile("isync;msync;tlbwe;isync");
42
43 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
44 /*
45 * TLB entry for debuggging in AS1
46 * Create temporary TLB entry in AS0 to handle debug exception
47 * As on debug exception MSR is cleared i.e. Address space is changed
48 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
49 * in AS1.
50 *
51 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
52 * bacause flash's physical address is going to change as
53 * CONFIG_SYS_FLASH_BASE_PHYS.
54 */
55 _mas0 = MAS0_TLBSEL(1) |
56 MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
57 _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT |
58 MAS1_TSIZE(BOOKE_PAGESZ_4M);
59 _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
60 _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
61 _mas7 = FSL_BOOKE_MAS7(flash_phys);
62
63 mtspr(MAS0, _mas0);
64 mtspr(MAS1, _mas1);
65 mtspr(MAS2, _mas2);
66 mtspr(MAS3, _mas3);
67 mtspr(MAS7, _mas7);
68
69 asm volatile("isync;msync;tlbwe;isync");
70 #endif
71
72 /* Change flash's physical address */
73 ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
74 ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
75 ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
76
77 return ;
78 }
79 #endif
80
81 /* We run cpu_init_early_f in AS = 1 */
cpu_init_early_f(void * fdt)82 void cpu_init_early_f(void *fdt)
83 {
84 u32 mas0, mas1, mas2, mas3, mas7;
85 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
86 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
87 #endif
88 #ifdef CONFIG_A003399_NOR_WORKAROUND
89 ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
90 u32 *dst, *src;
91 void (*setup_ifc_sram)(void);
92 int i;
93 #endif
94
95 /* Pointer is writable since we allocated a register for it */
96 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
97
98 /* gd area was zeroed during startup */
99
100 #ifdef CONFIG_ARCH_QEMU_E500
101 /*
102 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
103 * so we need to populate it before it accesses it.
104 */
105 gd->fdt_blob = fdt;
106 #endif
107
108 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
109 mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
110 mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
111 mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
112 mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
113
114 write_tlb(mas0, mas1, mas2, mas3, mas7);
115
116 /*
117 * Work Around for IFC Erratum A-003549. This issue is P1010
118 * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC
119 * Hence specifically selecting CS3.
120 */
121 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
122 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
123 #endif
124
125 init_laws();
126
127 /*
128 * Work Around for IFC Erratum A003399, issue will hit only when execution
129 * from NOR Flash
130 */
131 #ifdef CONFIG_A003399_NOR_WORKAROUND
132 #define SRAM_BASE_ADDR (0x00000000)
133 /* TLB for SRAM */
134 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
135 mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
136 MAS1_TSIZE(BOOKE_PAGESZ_1M);
137 mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I);
138 mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR);
139 mas7 = FSL_BOOKE_MAS7(0);
140
141 write_tlb(mas0, mas1, mas2, mas3, mas7);
142
143 out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
144
145 out_be32(&l2cache->l2errdis,
146 (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
147
148 out_be32(&l2cache->l2ctl,
149 (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
150
151 /*
152 * Copy the code in setup_ifc to L2SRAM. Do a word copy
153 * because NOR Flash on P1010 does not support byte
154 * access (Erratum IFC-A002769)
155 */
156 setup_ifc_sram = (void *)SRAM_BASE_ADDR;
157 dst = (u32 *) SRAM_BASE_ADDR;
158 src = (u32 *) setup_ifc;
159 for (i = 0; i < 1024; i++) {
160 /* cppcheck-suppress nullPointer */
161 *dst++ = *src++;
162 }
163
164 /* cppcheck-suppress nullPointer */
165 setup_ifc_sram();
166
167 /* CLEANUP */
168 clrbits_be32(&l2cache->l2ctl,
169 (MPC85xx_L2CTL_L2E |
170 MPC85xx_L2CTL_L2SRAM_ENTIRE));
171 out_be32(&l2cache->l2srbar0, 0x0);
172 #endif
173
174 invalidate_tlb(1);
175
176 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \
177 !(defined(CONFIG_SPL_INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \
178 !defined(CONFIG_NAND_SPL)
179 disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB);
180 #endif
181
182 init_tlbs();
183 }
184