1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <config.h>
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/immap_85xx.h>
12*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define SRDS1_MAX_LANES 4
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static u32 serdes1_prtcl_map;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
19*4882a593Smuzhiyun [0] = {NONE, NONE, NONE, NONE},
20*4882a593Smuzhiyun [1] = {PCIE1, PCIE2, CPRI2, CPRI1},
21*4882a593Smuzhiyun [2] = {PCIE1, PCIE2, CPRI2, CPRI1},
22*4882a593Smuzhiyun [3] = {PCIE1, PCIE2, CPRI2, CPRI1},
23*4882a593Smuzhiyun [4] = {PCIE1, PCIE2, CPRI2, CPRI1},
24*4882a593Smuzhiyun [5] = {PCIE1, PCIE2, CPRI2, CPRI1},
25*4882a593Smuzhiyun [6] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
26*4882a593Smuzhiyun [7] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
27*4882a593Smuzhiyun [8] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
28*4882a593Smuzhiyun [9] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
29*4882a593Smuzhiyun [10] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
30*4882a593Smuzhiyun [11] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
31*4882a593Smuzhiyun [12] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
32*4882a593Smuzhiyun [13] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
33*4882a593Smuzhiyun [14] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
34*4882a593Smuzhiyun [15] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
35*4882a593Smuzhiyun [16] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
36*4882a593Smuzhiyun [17] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
37*4882a593Smuzhiyun [18] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
38*4882a593Smuzhiyun [19] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
39*4882a593Smuzhiyun [20] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
40*4882a593Smuzhiyun [21] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
41*4882a593Smuzhiyun [22] = {PCIE1, PCIE2, CPRI2, CPRI1},
42*4882a593Smuzhiyun [23] = {PCIE1, PCIE2, CPRI2, CPRI1},
43*4882a593Smuzhiyun [24] = {PCIE1, PCIE2, CPRI2, CPRI1},
44*4882a593Smuzhiyun [25] = {PCIE1, PCIE2, CPRI2, CPRI1},
45*4882a593Smuzhiyun [26] = {PCIE1, PCIE2, CPRI2, CPRI1},
46*4882a593Smuzhiyun [27] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
47*4882a593Smuzhiyun [28] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
48*4882a593Smuzhiyun [29] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
49*4882a593Smuzhiyun [30] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
50*4882a593Smuzhiyun [31] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
51*4882a593Smuzhiyun [32] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
52*4882a593Smuzhiyun [33] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
53*4882a593Smuzhiyun [34] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
54*4882a593Smuzhiyun [35] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
55*4882a593Smuzhiyun [36] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
56*4882a593Smuzhiyun [37] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
57*4882a593Smuzhiyun [38] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
58*4882a593Smuzhiyun [39] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
59*4882a593Smuzhiyun [40] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
60*4882a593Smuzhiyun [41] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
61*4882a593Smuzhiyun [42] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
62*4882a593Smuzhiyun [43] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
63*4882a593Smuzhiyun [44] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
64*4882a593Smuzhiyun [45] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
65*4882a593Smuzhiyun [46] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
66*4882a593Smuzhiyun [47] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
is_serdes_configured(enum srds_prtcl prtcl)69*4882a593Smuzhiyun int is_serdes_configured(enum srds_prtcl prtcl)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun if (!(serdes1_prtcl_map & (1 << NONE)))
72*4882a593Smuzhiyun fsl_serdes_init();
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return (1 << prtcl) & serdes1_prtcl_map;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
fsl_serdes_init(void)77*4882a593Smuzhiyun void fsl_serdes_init(void)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
80*4882a593Smuzhiyun u32 pordevsr = in_be32(&gur->pordevsr);
81*4882a593Smuzhiyun u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
82*4882a593Smuzhiyun MPC85xx_PORDEVSR_IO_SEL_SHIFT;
83*4882a593Smuzhiyun int lane;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun if (serdes1_prtcl_map & (1 << NONE))
86*4882a593Smuzhiyun return;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
91*4882a593Smuzhiyun printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
92*4882a593Smuzhiyun return;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
96*4882a593Smuzhiyun enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
97*4882a593Smuzhiyun serdes1_prtcl_map |= (1 << lane_prtcl);
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* Set the first bit to indicate serdes has been initialized */
101*4882a593Smuzhiyun serdes1_prtcl_map |= (1 << NONE);
102*4882a593Smuzhiyun }
103