1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2012 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/fsl_serdes.h>
9*4882a593Smuzhiyun #include <asm/processor.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include "fsl_corenet2_serdes.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun struct serdes_config {
14*4882a593Smuzhiyun u8 protocol;
15*4882a593Smuzhiyun u8 lanes[SRDS_MAX_LANES];
16*4882a593Smuzhiyun };
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #ifdef CONFIG_ARCH_B4860
19*4882a593Smuzhiyun static struct serdes_config serdes1_cfg_tbl[] = {
20*4882a593Smuzhiyun /* SerDes 1 */
21*4882a593Smuzhiyun {0x01, {AURORA, AURORA, CPRI6, CPRI5,
22*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
23*4882a593Smuzhiyun {0x02, {AURORA, AURORA, CPRI6, CPRI5,
24*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
25*4882a593Smuzhiyun {0x04, {AURORA, AURORA, CPRI6, CPRI5,
26*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
27*4882a593Smuzhiyun {0x05, {AURORA, AURORA, CPRI6, CPRI5,
28*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
29*4882a593Smuzhiyun {0x06, {AURORA, AURORA, CPRI6, CPRI5,
30*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
31*4882a593Smuzhiyun {0x07, {AURORA, AURORA, CPRI6, CPRI5,
32*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
33*4882a593Smuzhiyun {0x08, {AURORA, AURORA, CPRI6, CPRI5,
34*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
35*4882a593Smuzhiyun {0x09, {AURORA, AURORA, CPRI6, CPRI5,
36*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
37*4882a593Smuzhiyun {0x0A, {AURORA, AURORA, CPRI6, CPRI5,
38*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
39*4882a593Smuzhiyun {0x0B, {AURORA, AURORA, CPRI6, CPRI5,
40*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
41*4882a593Smuzhiyun {0x0C, {AURORA, AURORA, CPRI6, CPRI5,
42*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
43*4882a593Smuzhiyun {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
44*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1}},
45*4882a593Smuzhiyun {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5,
46*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1}},
47*4882a593Smuzhiyun {0x12, {CPRI8, CPRI7, CPRI6, CPRI5,
48*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1}},
49*4882a593Smuzhiyun {0x29, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
50*4882a593Smuzhiyun CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} },
51*4882a593Smuzhiyun {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
52*4882a593Smuzhiyun CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
53*4882a593Smuzhiyun {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
54*4882a593Smuzhiyun CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
55*4882a593Smuzhiyun {0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
56*4882a593Smuzhiyun CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
57*4882a593Smuzhiyun {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
58*4882a593Smuzhiyun CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
59*4882a593Smuzhiyun {0x2F, {AURORA, AURORA,
60*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
61*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
62*4882a593Smuzhiyun {0x30, {AURORA, AURORA,
63*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
64*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1}},
65*4882a593Smuzhiyun {0x32, {AURORA, AURORA,
66*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
67*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1}},
68*4882a593Smuzhiyun {0x33, {AURORA, AURORA,
69*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
70*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1}},
71*4882a593Smuzhiyun {0x34, {AURORA, AURORA,
72*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
73*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1}},
74*4882a593Smuzhiyun {0x39, {AURORA, AURORA, CPRI6, CPRI5,
75*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
76*4882a593Smuzhiyun {0x3A, {AURORA, AURORA, CPRI6, CPRI5,
77*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
78*4882a593Smuzhiyun {0x3C, {AURORA, AURORA, CPRI6, CPRI5,
79*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
80*4882a593Smuzhiyun {0x3D, {AURORA, AURORA, CPRI6, CPRI5,
81*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
82*4882a593Smuzhiyun {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5,
83*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1}},
84*4882a593Smuzhiyun {0x5C, {AURORA, AURORA,
85*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
86*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
87*4882a593Smuzhiyun {0x5D, {AURORA, AURORA,
88*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
89*4882a593Smuzhiyun CPRI4, CPRI3, CPRI2, CPRI1} },
90*4882a593Smuzhiyun {}
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun static struct serdes_config serdes2_cfg_tbl[] = {
93*4882a593Smuzhiyun /* SerDes 2 */
94*4882a593Smuzhiyun {0x17, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
95*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
96*4882a593Smuzhiyun AURORA, AURORA, SRIO1, SRIO1} },
97*4882a593Smuzhiyun {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
98*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
99*4882a593Smuzhiyun AURORA, AURORA, SRIO1, SRIO1}},
100*4882a593Smuzhiyun {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
101*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
102*4882a593Smuzhiyun AURORA, AURORA, SRIO1, SRIO1}},
103*4882a593Smuzhiyun {0x2A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
104*4882a593Smuzhiyun SRIO2, SRIO2,
105*4882a593Smuzhiyun AURORA, AURORA, SRIO1, SRIO1} },
106*4882a593Smuzhiyun {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
107*4882a593Smuzhiyun SRIO2, SRIO2,
108*4882a593Smuzhiyun AURORA, AURORA, SRIO1, SRIO1}},
109*4882a593Smuzhiyun {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
110*4882a593Smuzhiyun SRIO2, SRIO2,
111*4882a593Smuzhiyun AURORA, AURORA,
112*4882a593Smuzhiyun SRIO1, SRIO1}},
113*4882a593Smuzhiyun {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
114*4882a593Smuzhiyun SGMII_FM1_DTSEC3, AURORA,
115*4882a593Smuzhiyun SRIO1, SRIO1, SRIO1, SRIO1} },
116*4882a593Smuzhiyun {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
117*4882a593Smuzhiyun SGMII_FM1_DTSEC3, AURORA,
118*4882a593Smuzhiyun SRIO1, SRIO1, SRIO1, SRIO1}},
119*4882a593Smuzhiyun {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
120*4882a593Smuzhiyun SGMII_FM1_DTSEC3, AURORA,
121*4882a593Smuzhiyun SRIO1, SRIO1, SRIO1, SRIO1}},
122*4882a593Smuzhiyun {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
123*4882a593Smuzhiyun SGMII_FM1_DTSEC3, AURORA,
124*4882a593Smuzhiyun SRIO1, SRIO1, SRIO1, SRIO1}},
125*4882a593Smuzhiyun {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
126*4882a593Smuzhiyun SGMII_FM1_DTSEC3, AURORA,
127*4882a593Smuzhiyun SRIO1, SRIO1, SRIO1, SRIO1}},
128*4882a593Smuzhiyun {0x79, {SRIO2, SRIO2, SRIO2, SRIO2,
129*4882a593Smuzhiyun SRIO1, SRIO1, SRIO1, SRIO1} },
130*4882a593Smuzhiyun {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
131*4882a593Smuzhiyun SRIO1, SRIO1, SRIO1, SRIO1}},
132*4882a593Smuzhiyun {0x83, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
133*4882a593Smuzhiyun SRIO2, SRIO2, AURORA, AURORA,
134*4882a593Smuzhiyun XFI_FM1_MAC9, XFI_FM1_MAC10} },
135*4882a593Smuzhiyun {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
136*4882a593Smuzhiyun SRIO2, SRIO2, AURORA, AURORA,
137*4882a593Smuzhiyun XFI_FM1_MAC9, XFI_FM1_MAC10}},
138*4882a593Smuzhiyun {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
139*4882a593Smuzhiyun SRIO2, SRIO2, AURORA, AURORA,
140*4882a593Smuzhiyun XFI_FM1_MAC9, XFI_FM1_MAC10}},
141*4882a593Smuzhiyun {0x86, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
142*4882a593Smuzhiyun SRIO2, SRIO2,
143*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
144*4882a593Smuzhiyun XFI_FM1_MAC9, XFI_FM1_MAC10} },
145*4882a593Smuzhiyun {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
146*4882a593Smuzhiyun SRIO2, SRIO2,
147*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
148*4882a593Smuzhiyun XFI_FM1_MAC9, XFI_FM1_MAC10}},
149*4882a593Smuzhiyun {0x8C, {SRIO2, SRIO2, SRIO2, SRIO2,
150*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
151*4882a593Smuzhiyun XFI_FM1_MAC9, XFI_FM1_MAC10} },
152*4882a593Smuzhiyun {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
153*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
154*4882a593Smuzhiyun XFI_FM1_MAC9, XFI_FM1_MAC10}},
155*4882a593Smuzhiyun {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
156*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
157*4882a593Smuzhiyun XAUI_FM1_MAC10, XAUI_FM1_MAC10,
158*4882a593Smuzhiyun XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
159*4882a593Smuzhiyun {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
160*4882a593Smuzhiyun XAUI_FM1_MAC10, XAUI_FM1_MAC10,
161*4882a593Smuzhiyun XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
162*4882a593Smuzhiyun {0x9A, {PCIE1, PCIE1,
163*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
164*4882a593Smuzhiyun XAUI_FM1_MAC10, XAUI_FM1_MAC10,
165*4882a593Smuzhiyun XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
166*4882a593Smuzhiyun {0xB1, {PCIE1, PCIE1, PCIE1, PCIE1,
167*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
168*4882a593Smuzhiyun XFI_FM1_MAC9, XFI_FM1_MAC10} },
169*4882a593Smuzhiyun {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
170*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
171*4882a593Smuzhiyun XFI_FM1_MAC9, XFI_FM1_MAC10}},
172*4882a593Smuzhiyun {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
173*4882a593Smuzhiyun XAUI_FM1_MAC9, XAUI_FM1_MAC9,
174*4882a593Smuzhiyun SRIO1, SRIO1, SRIO1, SRIO1}},
175*4882a593Smuzhiyun {0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
176*4882a593Smuzhiyun XAUI_FM1_MAC9, XAUI_FM1_MAC9,
177*4882a593Smuzhiyun XAUI_FM1_MAC10, XAUI_FM1_MAC10,
178*4882a593Smuzhiyun XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
179*4882a593Smuzhiyun {}
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun #endif
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun #ifdef CONFIG_ARCH_B4420
184*4882a593Smuzhiyun static struct serdes_config serdes1_cfg_tbl[] = {
185*4882a593Smuzhiyun {0x0D, {NONE, NONE, CPRI6, CPRI5,
186*4882a593Smuzhiyun CPRI4, CPRI3, NONE, NONE} },
187*4882a593Smuzhiyun {0x0E, {NONE, NONE, CPRI8, CPRI5,
188*4882a593Smuzhiyun CPRI4, CPRI3, NONE, NONE} },
189*4882a593Smuzhiyun {0x0F, {NONE, NONE, CPRI6, CPRI5,
190*4882a593Smuzhiyun CPRI4, CPRI3, NONE, NONE} },
191*4882a593Smuzhiyun {0x17, {NONE, NONE,
192*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
193*4882a593Smuzhiyun NONE, NONE, NONE, NONE} },
194*4882a593Smuzhiyun {0x18, {NONE, NONE,
195*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
196*4882a593Smuzhiyun NONE, NONE, NONE, NONE} },
197*4882a593Smuzhiyun {0x1B, {NONE, NONE,
198*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
199*4882a593Smuzhiyun NONE, NONE, NONE, NONE} },
200*4882a593Smuzhiyun {0x1D, {NONE, NONE, AURORA, AURORA,
201*4882a593Smuzhiyun NONE, NONE, NONE, NONE} },
202*4882a593Smuzhiyun {0x1E, {NONE, NONE, AURORA, AURORA,
203*4882a593Smuzhiyun NONE, NONE, NONE, NONE} },
204*4882a593Smuzhiyun {0x21, {NONE, NONE, AURORA, AURORA,
205*4882a593Smuzhiyun NONE, NONE, NONE, NONE} },
206*4882a593Smuzhiyun {0x3E, {NONE, NONE, CPRI6, CPRI5,
207*4882a593Smuzhiyun CPRI4, CPRI3, NONE, NONE} },
208*4882a593Smuzhiyun {}
209*4882a593Smuzhiyun };
210*4882a593Smuzhiyun static struct serdes_config serdes2_cfg_tbl[] = {
211*4882a593Smuzhiyun {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
212*4882a593Smuzhiyun SGMII_FM1_DTSEC3, AURORA,
213*4882a593Smuzhiyun NONE, NONE, NONE, NONE} },
214*4882a593Smuzhiyun {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
215*4882a593Smuzhiyun SGMII_FM1_DTSEC3, AURORA,
216*4882a593Smuzhiyun NONE, NONE, NONE, NONE} },
217*4882a593Smuzhiyun {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
218*4882a593Smuzhiyun SGMII_FM1_DTSEC3, AURORA,
219*4882a593Smuzhiyun NONE, NONE, NONE, NONE} },
220*4882a593Smuzhiyun {0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
221*4882a593Smuzhiyun AURORA, AURORA, NONE, NONE, NONE, NONE} },
222*4882a593Smuzhiyun {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
223*4882a593Smuzhiyun AURORA, AURORA, NONE, NONE, NONE, NONE} },
224*4882a593Smuzhiyun {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
225*4882a593Smuzhiyun AURORA, AURORA, NONE, NONE, NONE, NONE} },
226*4882a593Smuzhiyun {0x99, {PCIE1, PCIE1,
227*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
228*4882a593Smuzhiyun NONE, NONE, NONE, NONE} },
229*4882a593Smuzhiyun {0x9A, {PCIE1, PCIE1,
230*4882a593Smuzhiyun SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
231*4882a593Smuzhiyun NONE, NONE, NONE, NONE} },
232*4882a593Smuzhiyun {0x9D, {PCIE1, PCIE1, PCIE1, PCIE1,
233*4882a593Smuzhiyun NONE, NONE, NONE, NONE} },
234*4882a593Smuzhiyun {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
235*4882a593Smuzhiyun NONE, NONE, NONE, NONE} },
236*4882a593Smuzhiyun {}
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun #endif
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun static struct serdes_config *serdes_cfg_tbl[] = {
241*4882a593Smuzhiyun serdes1_cfg_tbl,
242*4882a593Smuzhiyun serdes2_cfg_tbl,
243*4882a593Smuzhiyun };
244*4882a593Smuzhiyun
serdes_get_prtcl(int serdes,int cfg,int lane)245*4882a593Smuzhiyun enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
246*4882a593Smuzhiyun {
247*4882a593Smuzhiyun struct serdes_config *ptr;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
250*4882a593Smuzhiyun return 0;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun ptr = serdes_cfg_tbl[serdes];
253*4882a593Smuzhiyun while (ptr->protocol) {
254*4882a593Smuzhiyun if (ptr->protocol == cfg)
255*4882a593Smuzhiyun return ptr->lanes[lane];
256*4882a593Smuzhiyun ptr++;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun return 0;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
is_serdes_prtcl_valid(int serdes,u32 prtcl)262*4882a593Smuzhiyun int is_serdes_prtcl_valid(int serdes, u32 prtcl)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun int i;
265*4882a593Smuzhiyun struct serdes_config *ptr;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
268*4882a593Smuzhiyun return 0;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun ptr = serdes_cfg_tbl[serdes];
271*4882a593Smuzhiyun while (ptr->protocol) {
272*4882a593Smuzhiyun if (ptr->protocol == prtcl)
273*4882a593Smuzhiyun break;
274*4882a593Smuzhiyun ptr++;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun if (!ptr->protocol)
278*4882a593Smuzhiyun return 0;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun for (i = 0; i < SRDS_MAX_LANES; i++) {
281*4882a593Smuzhiyun if (ptr->lanes[i] != NONE)
282*4882a593Smuzhiyun return 1;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun return 0;
286*4882a593Smuzhiyun }
287